Causes Of Tco Smi - Intel 6300ESB Datasheet

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5—Intel 6300ESB ICH
Table 66. Causes of SMI# (Sheet 2 of 2)
Device Monitors matches an
address in its range
SMBus Host Controller
SMBus Slave SMI message
SMBus SMBALERT# signal
SMBus Host Notify message
Access to Microcontroller
Range (62h/66h)
SLP_EN bit written to 1
WDT 1
NOTES:
1. GBL_SMI_EN must be 1 to enable SMI.
2. EOS must be written to 1 to re-enable SMI for the next one.
3. Some SMI#s are considered "synchronous", in that the processor should recognize the SMI#
prior to completing the instruction (I/O read, I/O write, Memory read, or Memory write) that
should cause the SMI#. This is accomplished by having the SMI# signal go active to the
processor prior to the processor observing the RDY# signal that terminates the cycle. SMI#s
marked with X in the Synch column are treated as Synchronous.Synchronous SMI#s are not
possible in IA64 platforms, since they do not support the SMI# signal.
4. NMI2SMI_STS is not gated by TCO_EN.
Table 67.

Causes of TCO SMI#

Century Rollover
TCO TIMEROUT
OS writes to TCO_DAT_IN register
Message from MCH
NMI occurred (and NMIs mapped to
SMI)
See NMI section for causes of NMI
NOTE: NMI2SMI_STS is not gated by TCO_EN. See table above.
INTRUDER# signal goes active
Changes of the BIOSWP bit from 0
to 1
Write attempted to BIOS
Section 5.12.3, "TCO Theory of Operation"
See
causes.
November 2007
Order Number: 300641-004US
Cause Additional Enables
DEV[n]_TRAP_EN = 1
Host Controller enabled
active
HOST_NOTIFY_INTREN
received
SMI_ON_SLP_EN = 1
st
timeout
WDT_INT_TYPE = '10'
Cause
SMB_SMI_EN
None
None
HOST_NOTIFY_STS
MCSMI_EN
SMI_ON_SLP_EN_S
WDT_ENABLE = 1,
Additional Enables
None
None
None
None
NMI2SMI_EN = 1
INTRD_SEL = 10
BLD = 1
BIOSWP = 1
for details on the TCO SMI#
Where Reported Synch
DEVMON_STS,
DEV[n]_TRAP_STS
Various bits in the
SMBus Host Status
Register
SMBUS_SMI_STS
SMBUS_SMI_STS
SMBUS_SMI_STS,
MCSMI_STS
TS
WDT_SMI_STS
Where Reported
NEWCENTURY_STS
TIMEOUT
OS_TCO_SMI
MCHSMI_STS
NMI2SMI_STS
INTRD_DET
BIOSWR_STS
BIOSWR_STS
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Intel 6300ESB I/O Controller Hub
X
X
X
DS
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