Uhci Vs. Ehci; Usb Ehci Controller (D29:F7) - Intel 6300ESB Datasheet

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5—Intel 6300ESB ICH
Table 106. USB Legacy Keyboard State Transitions
Current
Action
State
GateState2 60h / Write
GateState2 60h / Read
NOTES:
1. If bit 7 of the Extended Test Mode Register 1 (D31:F0, offset F4h ETR1, section 9.1.36) is set. Port 60/64h
Reads and Writes from an external PCI agent will not affect set bits 8-11 and will not cause an SMI
independent of the setting of bits 0-3
2. System Software should ensure that the host controller and an external PCI agent are not simultaneously
executing keyboard accesses including an A20Gate Pass-through sequence to Port 60h & 64h. This is not
supported and the results may be indeterminate.
5.18

USB EHCI Controller (D29:F7)

5.18.1 Overview
The Intel
compliant host controller which supports up to four High-speed USB 2.0 Specification
compliant root ports. High-speed USB 2.0 allows data transfers up to 480 Mbps using
the same pins as the four Full-speed and Low-speed USB Universal Host Controller
Interface (UHCI) ports. The Intel
determines whether a USB port is controlled by one of the UHCI controllers or by the
EHCI controller. A USB 2.0 based Debug Port is also implemented in the Intel
6300ESB ICH.
A summary of the key architectural differences between the USB UHCI host controllers
and the USB EHCI host controller are shown in the table below:
Table 107. UHCI vs. EHCI
Accessible by
Memory Data Structure
Differential Signaling Voltage
Ports per Controller
5.18.2 EHC Initialization
The following descriptions step through the expected Intel
Host Controller (EHC) initialization sequence in chronological order, beginning with a
complete power cycle in which the suspend well and core well have been off.
November 2007
Order Number: 300641-004US
Data Next
Value State
XXh IDLE
N/A IDLE
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6300ESB ICH contains an Enhanced Host Controller Interface (EHCI)
Feature USB 1.1 UHCI
I/O space
Single linked list
3.3 V
2
Improper end of sequence. Bit 1 in Config Register
determines if cycle passed through to 8042 and if
SMI# generated. PSTATE goes to 0. When Bit 7 in
Config Register is set, then SMI# should be generated.
Improper end of sequence. Bit 0 in Config Register
determines if cycle passed through to 8042 and if
SMI# generated. PSTATE goes to 0. When Bit 7 in
Config Register is set, then SMI# should be generated.
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6300ESB ICH contains port-routing logic that
Memory Space
Separated into Periodic and Asynchronous
lists.
400 mV
4
Comment
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USB 2.0 EHCI
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6300ESB ICH Enhanced
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Intel 6300ESB I/O Controller Hub
DS
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