Offset 04H - 05H: Cmd-Command Register (Ide-D31:F1) - Intel 6300ESB Datasheet

®
9—Intel 6300ESB ICH
9.1.3 Offset 04h - 05h: CMD—Command Register (IDE—
D31:F1)
Table 325. Offset 04h - 05h: CMD—Command Register (IDE—D31:F1)
31
Device:
04h-05h
Offset:
00h
Default Value:
Bits Name
15:1
Reserved
1
10 Interrupt Disable (ID)
Fast Back to Back Enable
9
(FBE)
8 SERR# Enable
7 Wait Cycle Control
6 Parity Error Response
5 VGA Palette Snoop
Postable Memory Write
4
Enable (PMWE)
Special Cycle Enable
3
(SCE)
Bus Master Enable
2
(BME)
Memory Space Enable
1
(MSE)
IOSE - I/O Space Enable
0
(IOSE)
November 2007
Order Number: 300641-004US
Attribute:
Description
Reserved.
Enables the P-ATA host controller to assert the INTA# (in
native mode) or IRQ14/15 (in legacy mode). When set, the
interrupt will be deasserted. When cleared, the interrupt may
be asserted.
Reserved as '0'.
Reserved as '0'.
Reserved as '0'.
Reserved as '0'.
Reserved as '0'.
Reserved as '0'.
Reserved as '0'.
®
Controls the Intel 6300ESB ICH's ability to act as a PCI
master for IDE Bus Master transfers.
0 = Disables access.
1 = Enables access to the IDE Expansion memory range. The
EXBAR register (Offset 24h) must be programmed before
this bit is set.
NOTE: BIOS should set this bit to a 1.
This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both
Primary and Secondary) as well as the Bus Master IO
registers.
1 = Enable. The Base Address register for the Bus Master
registers should be programmed before this bit is set.
NOTES:
1. Separate bits are provided (IDE Decode Enable, in the IDE
Timing register) to independently disable the Primary or
Secondary I/O spaces.
2. When this bit is 0 and the IDE controller is in Native Mode,
the Interrupt Pin Register will be masked (the interrupt will
not be asserted) See Section 10.1.16, "Offset 60h:
USB_RELNUM—USB Release Number Register (USB—
D29:F0/F1)" for more information regarding the Interrupt
Pin Register. When an interrupt occurs while the masking
is in place and the interrupt is still active when the
masking ends, the interrupt will be allowed to be asserted.
1
Function:
Read-Only, Read/Write
16-bit
Size:
Intel
Access
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
®
6300ESB I/O Controller Hub
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