Offset 6C - 6Fh: Usb Ehci Legacy Support Extended Control/Status - Intel 6300ESB Datasheet

11.1.26 Offset 6C - 6Fh: USB EHCI Legacy Support
Extended Control/Status
Table 404. Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status
(Sheet 1 of 2)
29
Device:
6C-6Fh
Offset:
00000000h
Default Value:
Bits Name
31 SMI on BAR
30 SMI on PCI Command
SMI on OS Ownership
29
Change
28:2
Reserved
2
21 SMI on Async Advance
SMI on Host System
20
Error
SMI on Frame List
19
Rollover
SMI on Port Change
18
Detect
17 SMI on USB Error
16 SMI on USB Complete
15 SMI on BAR Enable
SMI on PCI Command
14
Enable
SMI on OS Ownership
13
Enable
12:6 Reserved
SMI on Async Advance
5
Enable
®
Intel 6300ESB I/O Controller Hub
DS
500
Attribute:
Power Well:
Description
This bit is set to '1' whenever the Base Address Register
(BAR) is written.
This bit is set to '1' whenever the PCI Command Register is
written.
This bit is set to '1' whenever the HC OS Owned Semaphore
bit in the USB EHCI Legacy Support Extended Capability
register transitions from '1' to a '0' or '0' to a '1'.
Hardwired to 00h.
Shadow bit of the Interrupt on Async Advance bit in the
USB2STS register. To clear this bit system software must
write a '1' to the Interrupt on Async Advance bit in the
USB2STS register.
Shadow bit of Host System Error bit in the USB2STS. To clear
this bit, system software must write a '1' to the Host System
Error bit in the USB2STS register.
Shadow bit of Frame List Rollover bit in the USB2STS register.
To clear this bit system software must write a '1' to the Frame
List Rollover bit in the USB2STS register.
Shadow bit of Port Change Detect bit in the USB2STS register.
To clear this bit system software must write a '1' to the Port
Change Detect bit in the USB2STS register.
Shadow bit of USB Error Interrupt (USBERRINT) bit in the
USB2STS register. To clear this bit system software must
write a '1' to the USB Error Interrupt bit in the USB2STS
register.
Shadow bit of USB Interrupt (USBINT) bit in the USB2STS
register. To clear this bit system software must write a '1' to
the USB Interrupt bit in the USB2STS register.
When this bit is '1' and SMI on BAR is '1', the host controller
will issue an SMI.
When this bit is '1' and SMI on PCI Command is '1', the host
controller will issue an SMI.
When this bit is a '1' AND the OS Ownership Change bit is '1',
the host controller will issue an SMI.
Reserved—RO. Hardwired to 00h.
When this bit is a '1' and the SMI on Async Advance bit is a
'1', the host controller will issue an SMI immediately.
7
Function:
Read/Write
32-bit
Size:
Suspend
Order Number: 300641-004US
®
Intel 6300ESB ICH—11
Access
R/WC
R/WC
R/WC
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
R/W
November 2007