Intel 6300ESB Datasheet page 670

Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 3 of 3)
28
Device
3E
Offset
Bits Name
Modifies the response by the bridge to ISA I/O addresses.
This only applies to I/O addresses that are enabled by the I/O
Base and I/O Limit registers and are in the first 64 Kbytes of
PCI-X I/O space. When this bit is set, the bridge blocks any
ISA Enable
02 forwarding from primary to secondary of I/O transactions
(IE)
addressing the last 768 bytes in each 1 Kbyte block (offsets
100h to 3FFh). This bit has no effect on transfers originating
on the secondary bus as the Intel
forward I/O transactions across the bridge.
PXSERR#
01 When set, the bridge is enabled for SERR reporting.
Enable (SE)
Controls the Intel
Parity Error data parity errors on the secondary interface. When the bit is
Response cleared, the bridge must ignore any parity errors that it
0
Enable detects and continue normal operation. The Intel
(PERE) ICH must generate parity even when parity error reporting is
disabled.
®
Intel 6300ESB I/O Controller Hub
DS
670
Function
Attribute:
Description
®
6300ESB ICH does not
®
6300ESB ICH's response to address and
Intel
0
Read/Write
16-bit
Size:
Reset
Value
0
0
0
®
6300ESB
Order Number: 300641-004US
®
6300ESB ICH—18
Access
R/W
R/W
R/W
November 2007