Offset 2Eh - 2Fh: Sid-Subsystem Id (Smbus-D31:F2/F4); Offset 3Ch: Intr_Ln-Interrupt Line Register (Smbus-D31:F3); Offset 3Dh: Intr_Pn-Interrupt Pin Register (Smbus-D31:F3) - Intel 6300ESB Datasheet

12.1.11 Offset 2Eh - 2Fh: SID—Subsystem ID (SMBUS—
D31:F2/F4)
Table 435. Offset 2Eh - 2Fh: SID—Subsystem ID (SMBUS—D31:F2/F4)
31
Device:
2Eh-2Fh
Offset:
0000h
Default Value:
No
Lockable:
Bits Name
15:0 Subsystem ID (SID)
12.1.12 Offset 3Ch: INTR_LN—Interrupt Line Register
(SMBUS—D31:F3)
Table 436. Offset 3Ch: INTR_LN—Interrupt Line Register (SMBUS—D31:F3)
31
Device:
3Ch
Offset:
00h
Default Value:
Bits Name
7:0 Interrupt line
12.1.13 Offset 3Dh: INTR_PN—Interrupt Pin Register
(SMBUS—D31:F3)
Table 437. Offset 3Dh: INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)
31
Device:
3Dh
Offset:
02h
Default Value:
Bits Name
7:0 Interrupt PIN
®
Intel 6300ESB I/O Controller Hub
DS
532
Attribute:
Power Well:
Description
The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems
from each other. The value returned by reads from this
register is the same as that which was written by BIOS into
the IDE_SID register.
Attribute:
Description
This data is not used by the Intel
communicate to software that the interrupt line is connected
to PIRQB#.
Attribute:
Description
02h = Indicates that the Intel
Controller will drive PIRQB# as its interrupt line.
3
Function:
Read-Only
16-bit
Size:
Core
3
Function:
Read/Write
8-bit
Size:
®
6300ESB ICH. It is to
3
Function:
Read-Only
8-bit
Size:
®
6300ESB ICH SMBus
Order Number: 300641-004US
®
Intel 6300ESB ICH—12
Access
RO
Access
R/W
Access
RO
November 2007