Stop Frame Explanation; Data Frame Format - Intel 6300ESB Datasheet

®
5—Intel 6300ESB ICH
5.8.3 Stop Frame
After all data frames, a Stop Frame is driven by the Intel
signal is driven low by the Intel
clocks is determined by the SERIRQ configuration register. The number of clocks
determines the next mode:
Table 56.

Stop Frame Explanation

Stop Frame Width
2 PCI clocks
3 PCI clocks
5.8.4 Specific Interrupts Not Supported via SERIRQ
There are three interrupts seen through the serial stream which are not supported by
®
the Intel
sharable with other devices within the system. These interrupts are:
•
IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
•
IRQ8#. RTC interrupt may only be generated internally.
•
IRQ13. Floating point error interrupt generated off of the processor assertion of
FERR#.
The Intel
and will not adjust their level based on the level seen in the serial stream. In addition,
the interrupts IRQ14 and IRQ15 from the serial stream are treated differently than
their ISA counterparts. These two frames are not passed to the Bus Master IDE logic.
The Bus Master IDE logic expects IDE to be behind the Intel
5.8.5

Data Frame Format

Table 57
from the Intel
interrupt may be signaled through both the PCI interrupt input signal and through the
SERIRQ signal (they are shared).
Table 57. Data Frame Format (Sheet 1 of 2)
Data
Frame
#
1
2
3
4
5
6
7
8
November 2007
Order Number: 300641-004US
®
Quiet Mode. Any SERIRQ device may initiate a Start Frame
Continuous Mode. Only the host (Intel
Start Frame
6300ESB ICH. These interrupts are generated internally, and are not
®
6300ESB ICH will ignore the state of these interrupts in the serial stream,
shows the format of the data frames. For the PCI interrupts (A-D), the output
®
6300ESB ICH is ANDed with the PCI input signal. This way, the
Clocks Past
Interrupt Start
Frame
IRQ0 2
IRQ1 5
SMI# 8
IRQ3 11
IRQ4 14
IRQ5 17
IRQ6 20
IRQ7 23
6300ESB ICH for 2 or 3 PCI clocks. The number of
Next Mode
Comment
Ignored. IRQ0 may only be generated through the
internal 8524.
Before Port 60h latch
Causes SMI# when low. Will set the SERIRQ_SMI_STS
bit, (bit 15).
®
6300ESB ICH. The SERIRQ
®
6300ESB ICH) may initiate a
®
6300ESB ICH.
®
Intel 6300ESB I/O Controller Hub
DS
137