Intel 6300ESB Datasheet page 10

5.6.4.9
5.6.4.10 Automatic End of Interrupt Mode ............................................... 119
5.6.5 Masking Interrupts................................................................................ 119
5.6.5.1
5.6.5.2
5.6.6 Steering PCI Interrupts.......................................................................... 119
5.6.7 Special Handling of IRQ1 and IRQ12........................................................ 120
5.7 Advanced Interrupt Controller (APIC) (D29:F5).................................................... 121
5.7.1 Interrupt Handling ................................................................................ 121
5.7.2 SMI/NMI/INIT/ExtINT Delivery Modes...................................................... 121
5.7.3 Boot Interrupt ...................................................................................... 122
5.7.4 Interrupt Mapping................................................................................. 123
5.7.5 APIC Bus Functional Description.............................................................. 124
5.7.5.1
5.7.5.2
5.7.6 PCI Message-Based Interrupts ................................................................ 132
5.7.6.1
5.7.6.2
5.7.7 Processor System Bus Interrupt Delivery ................................................. 133
5.7.7.1
5.7.7.2
5.7.7.3
5.7.7.4
5.7.7.5
5.8 Serial Interrupt (D31:F0).................................................................................. 135
5.8.1 Start Frame ......................................................................................... 136
5.8.2 Data Frames ........................................................................................ 136
5.8.3 Stop Frame.......................................................................................... 137
5.8.4 Specific Interrupts Not Supported via SERIRQ........................................... 137
5.8.5 Data Frame Format............................................................................... 137
5.9 Real Time Clock (D31:F0) ................................................................................. 138
5.9.1 RTC Overview ...................................................................................... 138
5.9.1.1
5.9.1.2
5.9.1.3
5.9.1.4
5.9.1.5
5.10 Processor Interface (D31:F0) ............................................................................ 141
5.10.1 Processor Interface Signals .................................................................... 141
5.10.1.1 A20M# .................................................................................. 141
5.10.1.2 INIT# .................................................................................... 141
5.10.1.3 FERR#/IGNNE# (Coprocessor Error) .......................................... 142
5.10.1.4 NMI ....................................................................................... 143
5.10.1.5 STPCLK# and CPUSLP# Signals................................................. 143
5.10.2 Dual Processor Issues ........................................................................... 143
5.10.2.1 Signal Differences ................................................................... 143
5.10.2.2 Dual Processor Power Management............................................ 143
5.11 Power Management (D31:F0) ............................................................................ 145
5.11.1 Features .............................................................................................. 145
5.11.2 Intel
5.11.3 System Power Planes ............................................................................ 148
5.11.4 Intel
5.11.5 SMI#/SCI Generation............................................................................ 149
5.11.6 Dynamic Processor Clock Control ............................................................ 152
5.11.6.1 Throttling Using STPCLK#......................................................... 153
5.11.6.2 Transition Rules among S0/Cx and Throttling States .................... 153
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Intel 6300ESB I/O Controller Hub
DS
10
Normal End of Interrupt ........................................................... 119
Masking on an Individual Interrupt Request ................................ 119
Special Mask Mode .................................................................. 119
APIC Bus Arbitration ................................................................ 125
Bus Message Formats .............................................................. 126
Theory of Operation................................................................. 132
Registers and Bits Associated with PCI Interrupt Delivery ............. 133
Theory of Operation................................................................. 133
Edge-Triggered Operation......................................................... 134
Level-Triggered Operation ........................................................ 134
Registers Associated with Processor System Bus Interrupt Delivery 134
Interrupt Message Format ........................................................ 134
Update Cycles ......................................................................... 139
Interrupts .............................................................................. 139
Lockable RAM Ranges .............................................................. 139
Century Rollover ..................................................................... 139
Clearing Battery-Backed RTC RAM ............................................. 140
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6300ESB ICH Power States and Transition Rules ............................. 146
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6300ESB ICH Power Planes .......................................................... 148
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Intel 6300ESB ICH-Contents
November 2007
Order Number: 300641-004US