Offset Gpiobase + 00H: Gpio_Use_Sel-Gpio Use Select Register; Offset Gpiobase + 04H: Gp_Io_Sel-Gpio Input/Output Select Register - Intel 6300ESB Datasheet

8.10.2 Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO
Use Select Register
Table 314. Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register
31
Device:
GPIOBASE + 00h
Offset:
1B003100h
Default Value:
Yes
Lockable:
Bits Name
23,
21:1
GPIO_USE_SEL[0:7, 11,
6,
16:21, 23]
11,
7:0
8.10.3 Offset GPIOBASE + 04h: GP_IO_SEL—GPIO
Input/Output Select Register
Table 315. Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select
Register
31
Device:
GPIOBASE +04h
Offset:
0000FFFFh
Default Value:
No
Lockable:
Bits Name
31:2
Reserved
9, 26
28:2
7
GPIO[n]_SEL
25:2
4
23
®
Intel 6300ESB I/O Controller Hub
DS
426
Attribute:
Power Well:
Description
Enables GPIO[n] (where n is the bit number) to be used as a
GPIO, rather than for the native function.
1 = Signal used as GPIO (or unmuxed). 0 = Signal used as
native function.
Notes:
1. The following bits are not implemented because there is no
corresponding GPIO: 9:10, 14:15, 22,
26 and 29:31.
2. The following bits are always 1 because they are
unmuxed: 8, 12:13, 24, 25, 27:28.
3. When GPIO[n] does not exist, the bit in this register will
always read as 0 and writes will have no effect.
4. After a full reset (RSMRST#) all multiplexed signals in the
resume and core wells are configured as their native
function rather than as a GPIO. After just a PXPCIRST#,
the GPIO in the core well are configured as their native
function.
Attribute:
Power Well:
Description
Reserved.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Always 0. The GPIOs are fixed as outputs.
0
Function:
Read/Write
32-bit
Size:
Core for 0:7 and 16:21, 23
Resume for 8:15 and 24:31
0
Function:
Read-Only
32-bit
Size:
Resume
Order Number: 300641-004US
®
Intel 6300ESB ICH—8
Access
Access
R/W
November 2007