Intel 6300ESB Datasheet page 409

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8—Intel 6300ESB ICH
Table 293. SMI_STS—SMI Status Register (Sheet 2 of 2)
31
Device:
PMBASE + 34h
I/O Address:
00000000h
Default Value:
No
Lockable:
Bits Name
MCSMI_STS: Microcon-
11
troller SMI# Status
10 GPE1_STS
9 GPE0_STS
8 PM1_STS_REG
7 Reserved
6 SWSMI_TMR_STS
5 APM_STS
4 SLP_SMI_STS
3 LEGACY_USB_STS
2 BIOS_STS
1:0 Reserved
November 2007
Order Number: 300641-004US
Attribute:
Power Well:
Description
0 = Indicates that there has been no access to the power
management microcontroller range (62h or 66h). This bit
is cleared by software writing a 1 to the bit position.
1 = Set when there has been an access to the power
management microcontroller range (62h or 66h). When
this bit is set, and the MCSMI_EN bit is also set, the
®
Intel 6300ESB ICH will generate an SMI#.
This bit is a logical OR of the bits in the ALT_GP_SMI_STS
register that are also set up to cause an SMI# (as indicated
by the GPI_ROUT registers) and have the corresponding bit
set in the ALT_GP_SMI_EN register. Bits that are not routed
to cause an SMI# will have no effect on this bit.
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
This bit is a logical OR of the bits in the GPE0_STS register
that also have the corresponding bit set in the GPE0_EN
register.
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
This is an ORs of the bits in the ACPI PM1 Status Register
(offset PMBASE+00h) that may cause an SMI#.
0 = SMI# was not generated by a PM1_STS event.
1 = SMI# was generated by a PM1_STS event.
Reserved.
1 = Set by the hardware when the Software SMI# Timer
expires.
0 = Software clears this bit by writing a 1 to the bit location.
0 = Software clears this bit by writing a 1 to the bit location.
1 = SMI# was generated by a write access to the APM control
register with the APMC_EN bit set.
0 = Software clears this bit by writing a 1 to the bit location.
1 = Indicates an SMI# was caused by a write of 1 to SLP_EN
bit when SLP_SMI_EN bit is also set.
This bit is a logical OR of each of the SMI status bits in the
USB Legacy Keyboard/Mouse Control Registers ANDed with
the corresponding enable bits. This bit will not be active When
the enable bits are not set.
0 = SMI# was not generated by USB Legacy event.
1 = SMI# was generated by USB Legacy event.
0 = This bit cleared by software writing a 1 to its bit position.
1 = SMI# was generated due to ACPI software requesting
attention (writing a 1 to the GBL_RLS bit with the
BIOS_EN bit set).
Reserved.
0
Function:
Read/Write
32-bit
Size:
Core
Intel
Access
R/WC
RO
R/WC
R/WC
R/WC
R/WC
R/WC
RO
R/WC
®
6300ESB I/O Controller Hub
DS
409