Offset 0Bh: Base Class Code; Offset 0Dh: Master Latency Timer; Offset 10 - 13H: Memory Base Address - Intel 6300ESB Datasheet

11.1.6

Offset 0Bh: Base Class Code

Table 384. Offset 0Bh: Base Class Code
29
Device:
0Bh
Offset:
0Ch
Default Value:
Bits Name
7:0 Base Class Code
11.1.7

Offset 0Dh: Master Latency Timer

Table 385. Offset 0Dh: Master Latency Timer
29
Device:
0Dh
Offset:
00h
Default Value:
Bits Name
7:0 Master Latency Timer
11.1.8

Offset 10 - 13h: Memory Base Address

Table 386. Offset 10 - 13h: Memory Base Address
29
Device:
10 - 13h
Offset:
00000000h
Default Value:
Bits Name
31:1
Base Address
0
9:4 Reserved
3 Prefetchable
2:1 Type
Resource Type Indicator
0
(RTE)
®
Intel 6300ESB I/O Controller Hub
DS
490
Attribute:
Description
A value of 0Ch indicates that this is a Serial Bus controller.
Attribute:
Description
Since the USB EHCI controller is internally implemented with
arbitration through the Hub Interface (and not PCI), it does
not need a master latency timer. These bits will be fixed to 0.
Attribute:
Description
Bits [31:10] correspond to memory address signals [31:10],
respectively. This gives 1 Kbyte of locatable memory space
aligned to 1 Kbyte boundaries.
Reserved.
This bit is hardwired to 0, indicating that this range should
not be prefetched.
This field is hardwired to 00b indicating that this range may
be mapped anywhere within 32-bit address space.
This field is hardwired to 00b indicating that this range may
be mapped anywhere within 32-bit address space.
7
Function:
Read-Only
8-bit
Size:
7
Function:
Read-Only
8-bit
Size:
7
Function:
Read/Write
32-bit
Size:
Order Number: 300641-004US
®
Intel 6300ESB ICH—11
Access
RO
Access
RO
Access
RW
RO
RO
RO
November 2007