Type 0 Configuration Cycle Device Number Translation; Standard Pci Bus Configuration Mechanism - Intel 6300ESB Datasheet

5.1.6

Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based "configuration space" that allows each device to
contain up to eight functions with each function containing up to 256, 8-bit
configuration registers. The PCI specification defines two bus cycles to access the PCI
configuration space: Configuration Read and Configuration Write. Memory and I/O
spaces are supported directly by the processor. Configuration space is supported by a
mapping mechanism implemented within the Intel
ICH only supports Mechanism #1 as defined in the PCI specification.
Configuration cycles for PCI Bus #0 devices #2 through #31, and for PCI Bus numbers
greater than 0 will be sent towards the Intel
The Intel
Number and Subordinate Bus number registers of its P2P bridge to determine when the
configuration cycle is meant for Primary PCI or a downstream PCI bus.
5.1.6.1 Type 0 to Type 0 Forwarding
When a Type 0 configuration cycle is received on Hub Interface to any function other
than USB EHCI or AC'97, the Intel
then reclaims them. The Intel
communicate the Intel
When the Type 0 cycle on Hub Interface specifies any device number other than 29, 30
or 31, the Intel
during the corresponding transaction on PCI.
translation.
Table 30.

Type 0 Configuration Cycle Device Number Translation

Device # In Hub Interface Type 0
The Intel
cycles on the PCI bus. The Intel
cycle for configurations to the bus number matching the PCI bus. When the cycle is
targeting a device behind an external bridge, the Intel
cycle on the PCI bus.
5.1.6.2 Type 1 to Type 0 Conversion
When the bus number for the Type 1 configuration cycle matches the PCI (Secondary)
bus number, the Intel
1. For device numbers 0 through 15, only one bit of the PCI address [31:16] will be
set. When the device number is 0, AD[16] is set; when the device number is 1,
AD[17] is set; etc.
2. The Intel
Type 1 configurations cycles to Type 0 configuration cycles on PCI.
3. Address bits [10:1] will also be passed unchanged to PCI.
4. Address bit [0] will be changed to '0'.
®
Intel 6300ESB I/O Controller Hub
DS
96
®
6300ESB ICH compares the non-zero Bus Number with the Secondary Bus
®
®
6300ESB ICH device numbers in Type 0 configuration cycles.
®
6300ESB ICH will not set any address bits in the range AD[31:11]
Cycle
0 through 28
29
30
31
®
6300ESB ICH logic will generate single D-word configuration read and write
®
®
6300ESB ICH will convert the address as follows:
®
6300ESB ICH will always drive 0s on bits AD[15:11] when converting
®
6300ESB ICH. The Intel
®
6300ESB ICH from the host controller.
®
6300ESB ICH forwards these cycles to PCI and
6300ESB ICH uses address bits AD[15:13] to
Table 30 shows the device number
AD[31:11] During Address Phase of Type 0
0000000000000000_00000b
0000000000000000_00100b
0000000000000000_01000b
0000000000000000_10000b
6300ESB ICH will generate a Type 0 configuration
®
®
Intel 6300ESB ICH—5
®
6300ESB
Cycle on PCI
6300ESB ICH will run a Type 1
November 2007
Order Number: 300641-004US