Lpc Interface Signals; Interrupt Signals; Interrupt Interface - Intel 6300ESB Datasheet

3.7 LPC I/F
Table 9.

LPC Interface Signals

Name
LAD[3:0]
/ FWH[3:0]
LFRAME#
/
FWH[4]
LDRQ[1:0
]#
NOTE: All LPC/FWH signals are in the core well
3.8

Interrupt Interface

Table 10. Interrupt Signals (Sheet 1 of 2)
Name
SERIRQ
PIRQ[D:A]#
NOTE: The Interrupt signals are 5V tolerant except for PXIRQ [3:0]# / GPIO[36:33]
®
Intel 6300ESB I/O Controller Hub
DS
66
Typ
e
LPC Multiplexed Command, Address, Data: Internal pull-ups are
I/O
provided.
I/O LPC Frame: Indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: Used by LPC devices, such as
I
Super I/O chips, to request DMA or bus master access.
Type
Serial Interrupt Request: This pin implements the serial interrupt
I/O
protocol.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals
may be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in the Interrupt Steering section. Each PIRQx# line has a
separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC
in the following fashion:
I
PIRQ[A]# IRQ16
PIRQ[B]# IRQ17
PIRQ[C]# IRQ18
PIRQ[D]# IRQ19
This frees the legacy interrupts. These signals are 5V tolerant.
Intel
Description
Description
Order Number: 300641-004US
®
6300ESB ICH—3
November 2007