Timers (D31:F0) - Intel 6300ESB Datasheet

The peripheral must not assume that the host will be able to perform transfer sizes that
are larger than the size allowed for the DMA channel, and be willing to accept a SIZE
field that is smaller than what it may currently have buffered.
To that end, it is recommended that future devices which may appear on the LPC bus,
which require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus
mastering interface and not rely on the 8237.
5.5

8254 Timers (D31:F0)

The Intel
and functions associated with the 8254 timers are in the core well. The 8254 unit is
clocked by a 14.31818 MHz clock. The 14.31818 MHz clock will stop during the S3-S5
and G3 states.
5.5.1 Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is
typically programmed for Mode 3 operation. The counter produces a square wave with
a period equal to the product of the counter period (838 ns) and the initial count value.
The counter loads the initial count value one counter period after software writes the
count value to the counter I/O address. The counter initially asserts IRQ0 and
decrements the count value by two each counter period. The counter negates IRQ0
when the count value reaches zero. It then reloads the initial count value and again
decrements the initial count value by two each counter period. The counter then
asserts IRQ0 when the count value reaches zero, reloads the initial count value, and
repeats the cycle, alternately asserting and negating IRQ0.
5.5.2 Counter 1, Refresh Request Signal
Prior to ICH1, typically in ISA platforms, this counter provided the refresh request
signal. Today, it is still typically programmed for Mode 2 operation and only impacts the
period of the REF_TOGGLE bit in Port 61. The initial count value is loaded one counter
period after being written to the counter I/O address. The REF_TOGGLE bit will have a
square wave behavior (alternate between 0 and 1) and will toggle at a rate based on
the value in the counter.
Programming the counter to anything other than Mode 2 will result in undefined
behavior for the REF_TOGGLE bit. See
Control Register"
5.5.3 Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3
operation. The counter provides a speaker frequency equal to the counter clock
frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled
by a write to port 061h (see
for more information).
5.5.4 Timer Programming
The counter/timers are programmed in the following fashion:
®
Intel 6300ESB I/O Controller Hub
DS
110
®
6300ESB ICH contains three counters which have fixed uses. All registers
(D31:F0:61h:bit 4) for REF_TOGGLE bit details.
Section 8.7.1, "NMI_SC—NMI Status and Control Register"
Section 8.7.1, "NMI_SC—NMI Status and
®
Intel 6300ESB ICH—5
November 2007
Order Number: 300641-004US