Offset 02 - 03H: Did-Device Id Register (Lpc I/F-D31:F0); Offset 04 - 05H: Pcicmd-Pci Command Register (Lpc I/F-D31:F0) - Intel 6300ESB Datasheet

®
8—Intel 6300ESB ICH
8.1.2 Offset 02 - 03h: DID—Device ID Register (LPC I/
F—D31:F0)
Table 182. Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F0)
31
Device:
02-03h
Offset:
25A1h
Default Value:
No
Lockable:
Bits Name
15:0 Device ID Value
8.1.3 Offset 04 - 05h: PCICMD—PCI COMMAND Register
(LPC I/F—D31:F0)
Table 183. Offset 04 - 05h: PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
31
Device:
04-05h
Offset:
000Fh
Default Value:
No
Lockable:
Bits Name
15:1
Reserved
0
FBE: Fast Back to Back
9
Enable
SERR_EN: SERR#
8
Enable
7 WCC: Wait Cycle Control
PER: Parity Error
6
Response
5 VPS: VGA Palette Snoop
PMWE: Postable Memory
4
Write Enable
SCE: Special Cycle
3
Enable
2 BME: Bus Master Enable
MSE: Memory Space
1
Enable
0 IOE: I/O Space Enable
November 2007
Order Number: 300641-004US
Attribute:
Power Well:
Description
This is a 16-bit value assigned to the Intel
Bridge.
Attribute:
Power Well:
Description
Reserved.
Hardwired to 0.
0 = Disable.
1 = Enable. Allow SERR# to be generated.
Hardwired to 0.
0 = No action is taken when detecting a parity error.
1 = The processor will take normal action when a parity error
is detected.
Hardwired to 0
Hardwired to 0
Hardwired to 1.
Hardwired to 1 to indicate that bus mastering cannot be
disabled for function 0 (DMA/ISA Master)
Hardwired to 1 to indicate that memory space cannot be
disabled for Function 0 (LPC I/F)
Hardwired to 1 to indicate that the I/O space cannot be
disabled for function 0 (LPC I/F)
0
Function:
Read-Only
16-bit
Size:
Core
®
6300ESB ICH LPC
0
Function:
Read/Write
16-bit
Size:
Core
Intel
Access
Access
RO
RO
RO
RO
RO
RO
RO
®
6300ESB I/O Controller Hub
DS
313