Eoir-Eoi Register - Intel 6300ESB Datasheet

Table 576. IRQPA—IRQ Pin Assertion Register
29
Device:
Memory
FEC0_0020h
Address:
N/A
Default Value:
Bits Name
31:5 Reserved
4:0 IRQ Number
17.2.5 EOIR—EOI Register
The EOI register is present to provide a mechanism to maintain the level-triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written
to this register and compare them with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entry will be cleared.
Note: When there are multiple I/O Redirection entries, assign the same vector for more than
one interrupt input. Each of those entries will have the Remote_IRR bit reset to '0'. The
interrupt that was prematurely reset will not be lost because if its input remained active
when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced at a
later time. Only bits 7:0 are actually used. Bits 31:8 are ignored.
Table 577. EOIR—EOI Register
29
Device:
Memory
FEC0_0040h
Address:
N/A
Default Value:
Bits Name
31:8 Reserved
7:0 End of Interrupt (EOI)
®
Intel 6300ESB I/O Controller Hub
DS
642
Attribute:
Description
Reserved. To provide for future expansion, the processor
should always write a value of '0' to Bits 31:5.
Bits 4:0 written to this register contain the IRQ number for
this interrupt. The only valid values are 0-23.
Attribute:
Description
Reserved. To provide for future expansion, the processor
should always write a value of '0' to Bits 31:8.
Vector to be compared with vector field in the I/O redirection
table when an EOI is issued.
5
Function:
Write-Only
32-bit
Size:
5
Function:
Write-Only
32-bit
Size:
Order Number: 300641-004US
®
Intel 6300ESB ICH—17
Access
WO
Access
WO
November 2007