Offset 3E - 3Fh: Bridge_Cnt-Bridge Control Register (Hub-Pci-D30:F0) - Intel 6300ESB Datasheet

®
7—Intel 6300ESB ICH
7.1.24 Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control
Register (HUB-PCI—D30:F0)
Table 170. Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—
D30:F0)
(Sheet 1 of 3)
30
Device:
3E-3Fh
Offset:
0000h
Default Value:
Bits Name
15:1
Reserved
1
12 PERR# to SERR# Enable
Discard Timer SERR#
11
Enable (DTSE)
Discard Timer Status
10
(DTS)
Secondary Discard
9
Timer (SDT)
Primary Discard
8
Timer (PDT)
7 Fast Back to Back Enable
November 2007
Order Number: 300641-004US
Attribute:
Description
Reserved.
When this bit is set to '1' PCI PERR NMI reporting is enabled.
In addition to setting this bit, you also must set bit 1 of
D30_F0 PNE Register. Section 7.1.28
When this bit is set to a '1' and PERR# is asserted on PCI, the
PERR# Assertion detect status bit (in the Secondary Status
Register) will indicate a PERR# internal SERR# assertion. The
SERR# can be a s source on NMI.
Controls the generation of SERR# on the primary interface in
response to a timer discard on the secondary interface:
• When '0': Do not generate SERR# on a secondary timer
discard
• When '1': Generate SERR# in response to a secondary
timer discard.
This bit replaces bit 1 of offset 90h, which held this function in
ICH3.
This bit is set to a '1' when the secondary discard timer
expires (there is no discard timer for the primary interface).
This bit replaces bit 1 of offset 92h, which held this function in
ICH3.
Sets the maximum number of PCI clock cycles that the Intel
6300ESB ICH waits for an initiator on PCI to repeat a delayed
transaction request. The counter starts once the delayed
transaction completion is at the head of the queue. When the
master has not repeated the transaction at least once before
the counter expires, the Intel
transaction from its queue.
• When '0': The PCI master timeout value is between 2
16
and 2 PCI clocks
• When '1': The PCI master timeout value is between 2
11
and 2 PCI clocks
This bit is RW for software compatibility only.
Hardwired to '0'. The PCI logic will not generate fast back-to-
back cycles on the PCI bus.
0
Function:
Read/Write
16-bit
Size:
®
6300ESB ICH discards the
Intel
Access
RW
R/W
R/W
®
R/W
15
10
R/W
®
6300ESB I/O Controller Hub
DS
301