Intel 6300ESB Datasheet page 718

occurs only when the erroneous byte is at the top of the FIFO. If the erroneous byte
being received is not at the top of the FIFO, an interrupt is generated only after the
previous bytes are read and the erroneous byte is moved to the top of the FIFO.
Table 646. Line Status Register (LSR) (Sheet 1 of 2)
Line Status Register
LSR
read-only
Bit Number
7
6
5
4
®
Intel 6300ESB I/O Controller Hub
DS
718
Address:
Reset State:
Access:
Bit Mnemonic
FIFO Error Status: In non-FIFO mode, this bit is 0. In FIFO
Mode, FIFOE is set to '1' when there is at least one parity error,
framing error, or break indication for any of the characters in the
FIFO. Note that a processor read to the Line Status register does
FIFOE
not reset this bit. FIFOE is reset when all error bytes have been
read from the FIFO. FIFOE set to '1' does not generate interrupt.
0 = No FIFO or no errors in receiver FIFO.
1 = At least one character in receiver FIFO has errors.
Transmitter Empty: TEMT is set to a logic '1' when the Transmit
Holding register and the Transmitter Shift register are both
empty. It is reset to a logic '0' when either the Transmit Holding
TEMT
register or the transmitter shift register contains a data character.
In FIFO mode, TEMT is set to '1' when the transmitter FIFO and
the Transmit Shift register are both empty.
Transmit Data Request: TDRQ indicates that the UART is ready
to accept a new character for transmission. In addition, this bit
causes the UART to issue an interrupt to the processor when the
transmit data request interrupt enable is set high and generates
the DMA request to DMA controller to ask for data. The TDRQ bit
is set to a logic '1' when a character is transferred from the
Transmit Holding register into the Transmit Shift register. The bit
is reset to logic '0' concurrently with the loading of the Transmit
Holding register by the processor. In FIFO mode, TDRQ is set to
TRDQ
'1' when the transmit FIFO is empty or the RESETTF bit in FCR
has been set to 1. It is cleared when at least one byte is written
to the transmit FIFO. If more than 16 characters are loaded into
the FIFO, the excess characters are lost.
0 = Processor has loaded the Transmit Holding Register.
1 = Transmit FIFO is empty (FIFO mode) or a character has
transferred from the Transmit Holding register into the Transmit
Shift register.
Break Interrupt: BI is set to a logic '1' when the received data
input is held in the spacing (logic 0) state for longer than a full
word transmission time (that is, the total time of Start bit + data
bits + parity bit + stop bits). The Break indicator is reset when
the processor reads the Line Status Register. In FIFO mode, only
one character (equal to 00H), is loaded into the FIFO regardless
BI
of the length of the break condition. BI shows the break condition
for the character at the top of the FIFO, not the most recently
received character.
0 = No break signal has been received.
1 = Break signal occurred
Intel
Base + 05H
60H
8-bit
Function
Order Number: 300641-004US
®
6300ESB ICH—19
November 2007