Ultra Ata Timing (Mode 3, Mode 4, Mode 5) - Intel 6300ESB Datasheet

Table 719. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 1 of 2)
Parameter (1)
Sym
t80 Sustained Cycle Time (T2cyctyp)
t81 Cycle Time (Tcyc)
t82 Two Cycle Time (T2cyc)
t83 Data Setup Time (Tds)
Recipient IC data setup time
t83b (from data valid until STROBE
edge) (see Note
t84 Data Hold Time (Tdh)
Recipient IC data hold time (from
STROBE edge until data may
t84b
become invalid) (see
(Tdhic)
t85 Data Valid Setup Time (Tdvs)
Sender IC data valid setup time
(from data valid until STROBE
t85b
edge) (
see Note 2) (Tdvsic)
t86 Data Valid Hold Time (Tdvh)
Sender IC data valid hold time
(from STROBE edge until data
t86b
may become invalid) (see
(Tdvhic)
t87 Limited Interlock Time (Tli)
t88 Interlock Time w/ Minimum (Tmli)
t89 Envelope Time (Tenv)
t90 Ready to Pause Time (Trp)
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/
ATAPI - 6) specification name.
2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on
measuring these timing parameters.
®
Intel 6300ESB I/O Controller Hub
DS
804
Mode 3
(ns)
Min
90
39
86
7
6.8
2) (Tdsic)
5
4.8
Note 2)
20
22.6
6.2
9.0
Note 2)
0
20
20
100
Mode 4 Mode 5
(ns) (ns)
Max Min Max Min
60 40
25 16.8
57 38
5 4.0
4.8 2.3
5 4.6
4.8 2.8
6.7 4.8
9.5 6.0
6.2 4.8
9.0 6.0
100 0 100 0
20 20
55 20 55 20
100 85
®
Intel 6300ESB ICH—22
Measuring
Figure
Location
Max
Sender
Connector
End
Figure 5
Recipient
3
Connector
Sender Figure 5
Connector 3
Recipient Figure 5
Connector 3
®
Intel
6300ESB
ICH Balls
Recipient Figure 5
Connector 3
®
Intel
6300ESB
ICH Balls
Figure 5
2
Sender
Connector
Figure 5
3
®
Intel
6300ESB
ICH Balls
Figure 5
2
Sender
Connector
Figure 5
3
®
Intel
6300ESB
ICH Balls
Figure 5
75 See Note 2
5
Host Figure 5
Connector 5
Host Figure 5
50
Connector 3
Recipient Figure 5
Connector 4
November 2007
Order Number: 300641-004US