Offset 06 - 07H: Device Status - Intel 6300ESB Datasheet

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11—Intel 6300ESB ICH
11.1.2

Offset 06 - 07h: Device Status

Table 380. Offset 06 - 07h: Device Status
29
Device:
06 - 07h
Offset:
0290h
Default Value:
Bits Name
Detected Parity Error
15
(DPE)
Signaled System Error
14
(SSE)
Received Master-Abort
13
Status (RMA)
Received Target Abort
12
Status (RTA)
Signaled Target-Abort
11
Status (STA)
DEVSEL# Timing Status
10:9
(DEVT)
Master Data Parity Error
8
Detected
Fast Back-to-Back
7
Capable
UDF - User Definable
6
Features
5 66 MHz Capable
4 Capabilities List
3:0 Reserved
November 2007
Order Number: 300641-004US
Attribute:
Description
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This bit is set by the Intel
error is seen on the internal interface to the USB host
controller due to a parity error on Hub Interface, regardless
of the setting of bit 6 or bit 8 in the Command register or any
other conditions. Software clears this bit by writing a '1' to
this bit location. Note that the Parity Error Response bit in the
HL-to-PCI bridge should be set in order for the Hub Interface
parity errors to be forwarded to the USB2 interface. This is a
result of the point-to-point nature of the Hub Interface
0 = Software clears this bit by writing a '1' to this bit location.
1 = This bit is set by the Intel
signals SERR# (internally). The SER_EN bit (bit 8 of the
Command Register) must be '1' for this bit to be set.
0 = Software clears this bit by writing a '1' to this bit location.
1 = This bit is set when USB EHCI, as a master, receives a
master-abort status on a memory access. This is treated
as a Host Error and halts the DMA engines. This event
may optionally generate an SERR# by setting the SERR#
.
Enable bit
0 = Software clears this bit by writing a '1' to this bit location.
1 = This bit is set when USB EHCI, as a master, receives a
target abort status on a memory access. This is treated
as a Host Error and halts the DMA engines. This event
may optionally generate an SERR# by setting the SERR#
.
Enable bit
This bit is used to indicate when the USB EHCI function
responds to a cycle with a target abort. There is no reason for
this to happen, so this bit will be hard-wired to '0'.
This 2-bit field defines the timing for DEVSEL# assertion.
0 = Software clears this bit by writing a '1' to this bit location.
1 = This bit is set by the Intel
data parity error is detected on a USB EHCI read
completion packet on the internal interface to the USB
EHCI host controller (due to an equivalent data parity
error on Hub Interface) and bit 6 of the Command
register is set to 1.
Reserved as 1.
Reserved as 0.
Reserved as 0.
This bit is hardwired to '1' indicating the presence of a valid
capabilities pointer at offset 34h.
Reserved.
7
Function:
Read/ Write
16-bit
Size:
6300ESB ICH whenever a parity
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6300ESB ICH whenever it
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6300ESB ICH whenever a
Intel
Access
R/W
R/W
R/W
R/W
RO
RO
R/W
RO
RO
RO
RO
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6300ESB I/O Controller Hub
DS
487