Intel 6300ESB Datasheet page 454

Table 345. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1) (Sheet 2 of 2)
31
Device:
4A - 4Bh
Offset:
0000h
Default Value:
Bits Name
Primary Drive 1 Cycle
5:4
Time (PCT1)
3:2 Reserved
Primary Drive 0 Cycle
1:0
Time (PCT0)
®
Intel 6300ESB I/O Controller Hub
DS
454
Attribute:
Description
For Synchronous DMA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The
DMARDY#-to-STOP (RP) time is also determined by the
setting of these bits.
PCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
Reserved.
For Synchronous DMA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The
DMARDY#-to-STOP (RP) time is also determined by the
setting of these bits.
PCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
1
Function:
Read/Write
16-bit
Size:
Order Number: 300641-004US
®
Intel 6300ESB ICH—9
Access
R/W
R/W
November 2007