Offset A0H: Gen_Pmcon_1-General Pm Configuration 1 Register (Pm-D31:F0) - Intel 6300ESB Datasheet

®
8—Intel 6300ESB ICH
8.8.1.1 Offset A0h: GEN_PMCON_1—General PM Configuration 1
Register
(PM—D31:F0)
Note: Usage: ACPI or Legacy.
Table 272. Offset A0h: GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)
31
Device:
A0h
Offset:
00h
Default Value:
No
Lockable:
Bits Name
15:1
Reserved
1
10 Reserved
9 PWRBTN_LVL
8:6 Reserved
CPUSLP_EN: CPU SLP#
5
Enable
4 SMI_LOCK
3:2 Reserved
PER_SMI_SEL: Periodic
1:0
SMI# rate Select
November 2007
Order Number: 300641-004US
Attribute:
Power Well:
Description
Reserved.
Reserved.
This read-only bit indicates the current state of the PWRBTN#
signal.
0 = Low.
1 = High.
Reserved.
0 = Disable.
1 = Enables the CPUSLP# signal to go active in the S1-D
states. This reduces the processor power.
Note that CPUSLP# will go active on entry to S3, S4 and S5
even when this bit is not set.
When this bit is set, writes to the GLB_SMI_EN bit will have
no effect Once the SMI_LOCK bit is set, writes of 0 to
SMI_LOCK bit will have no effect (i.e. once set, this bit may
only be cleared by PXPCIRST#).
Reserved.
Set by software to control the rate at which periodic SMI# is
generated.
00 = 64 seconds
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
0
Function:
Read/Write
16-bit
Size:
Core
Intel
Access
RO
R/W
R/WO
R/W
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