18.6.1.3 Offset 04: Cmd-Command - Intel 6300ESB Datasheet

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18—Intel 6300ESB ICH
18.6.1.3 Offset 04: CMD—Command
This controls how the device behaves on the primary interface and is the same as all
other devices, with the exception of the VGA Palette Snoop bit. As this component is a
bridge, additional command information is located in a separate register called "Bridge
Control" located at offset 3E.
Table 586. Offset 04: CMD—Command (Sheet 1 of 2)
28
Device
04
Offset
Bits Name
15:1
Reserved Reserved.
0
Fast Back-
to-back This bit has no meaning on the Hub Interface. It is hardwired
09
enable to '0'.
(FBE)
Controls the enable for assertion of SERR# (via NMI/SMI#)
when the SSE bit (D28:F0:Offset 06h, bit 14) is set. See
SERR#
Section 5.1.4
08 Enable
(SEE) 0 = SERR# disabled
1 = SERR# enabled
Wait Cycle
07 Control Reserved.
(WCC)
Controls the Intel
error is detected on the Hub Interface.
0 = The Intel
Parity Error
Response
06
1 = The Intel
Enable
(PERE)
NOTE: The Hub Interface Parity Unsupported bit
VGA Palette
Snoop
05 Reserved.
Enable
(VGA_PSE)
Memory
Write and The Intel
04 Invalidate and invalidate transactions, as the Hub Interface does not
Enable have a corresponding transfer type.
(MWIE)
Special
Cycle
03 Reserved.
Enable
(SCE)
November 2007
Order Number: 300641-004US
Description
for more details on this bit.
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6300ESB ICH's response when a parity
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6300ESB ICH ignores these errors on the Hub
Interface.
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6300ESB ICH reports these errors on the Hub
Interface and sets the DPD bit in the status register.
(D30:F0:40h:bit 20) must be cleared for the PER bit
to have any effect.
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6300ESB ICH does not generate memory write
0
Function
Read/Write
Attribute:
16-bit
Size:
Intel
Reset
Access
Value
00h RO
0 RO
0 R/W
0 RO
0 R/W
0 RO
0 RO
0 RO
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6300ESB I/O Controller Hub
DS
655