Offset 06 - 07H: Pd_Sts-Primary Device Status Register (Hub-Pci-D30:F0) - Intel 6300ESB Datasheet

7.1.4 Offset 06 - 07h: PD_STS—Primary Device Status
Register (HUB-PCI—D30:F0)
Note: For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit
will have no effect.
Table 150. Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—
D30:F0)
30
Device:
06-07h
Offset:
0080h
Default Value:
Bits Name
Detected Parity Error
15
(DPE)
Signaled System Error
14
(SSE)
Received Master Abort
13
(RMA)
Received Target Abort
12
(RTA)
Signaled Target Abort
11
(STA)
10:9 DEVSEL# Timing Status
Master Data Parity Error
8
Detected (MDPD)
7 Fast Back to Back
User Definable Features
6
(UDF)
5 66 MHz Capable
4:0 Reserved
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Intel 6300ESB I/O Controller Hub
DS
290
Attribute:
Description
0 = Software clears this bit by writing a '1' to the bit location.
1 = Indicates that the Intel
error on the Hub Interface and the Hub Interface Parity
Unsupported bit is cleared (D30:F0:40h:bit20). This bit
gets set even when the Parity Error Response bit (offset
04, bit 6) is not set.
0 = Software clears this bit by writing a '1' to the bit location.
1 = An address, or command parity error, or special cycles
data parity error has been detected on the PCI bus, and
the Parity Error Response bit (D30:F0, Offset 04h, bit 6)
is set. When this bit is set because of parity error and the
D30:F0 SERR_EN bit (Offset 04h, bit 8) is also set, the
®
Intel 6300ESB ICH will generate an NMI (or SMI# if NMI
routed to SMI#).
0 = Software clears this bit by writing a '1' to the bit location.
®
1 = The Intel 6300ESB ICH received a master abort from
the Hub Interface device.
0 = Software clears this bit by writing a '1' to the bit location.
®
1 = The Intel 6300ESB ICH received a target abort from the
Hub Interface device. The setting of this bit can be
enabled to cause an internal SERR#.
0 = Software clears this bit by writing a '1' to the bit location.
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1 = The Intel 6300ESB ICH signals a target abort condition
on the Hub Interface.
00h = Fast timing. This register applies to the Hub Interface.
Since this register applies to the Hub Interface, the Intel
6300ESB ICH must interpret this bit differently than it is in
the PCI spec.
0 = Software clears this bit by writing a '1' to the bit location.
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1 = The Intel 6300ESB ICH detects a parity error on the
Hub Interface and the Parity Error Response bit in the
Command Register (offset 04h, bit 6) is set.
Hardwired to '1'.
Hardwired to '0'.
Hardwired to '0'.
Reserved.
0
Function:
Read/Write Clear
16-bit
Size:
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6300ESB ICH detected a parity
Order Number: 300641-004US
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Intel 6300ESB ICH—7
Access
R/WC
R/WC
R/WC
R/WC
R/WC
RO
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R/WC
RO
RO
RO
November 2007