Intel 6300ESB Datasheet page 166

I/o controller hub

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1. Traditional designs have a reset button logically ANDs with the PWROK signal from

the power supply and the processor's voltage regulator module. When this is done

with the Intel

ICH treats this internally as though the RSMRST# signal had gone active. However,

it is not treated as a full power failure. When PWROK goes inactive and then active

(but RSMRST# stays high), then the Intel

the state of the AFTERG3 bit). When the RSMRST# signal also goes low before

PWROK goes high, then this is a full power failure and the reboot policy is

controlled by the AFTERG3 bit.

2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that

are less than one RTC clock period may not be detected by the Intel

5.11.11.3VRMPWRGD Signal

The VRMPWRGD signal is not implemented in the Intel

need to be pulled up to Vcc in order to disable internal legacy logic. If not pulled up,

this logic may come up in an unknown state.

6300ESB I/O Controller Hub

6300ESB ICH, the PWROK_FLR bit will be set. The Intel

6300ESB ICH will reboot (regardless of

6300ESB ICH. VRMPWRGD

Order Number: 300641-004US

6300ESB ICH—5

November 2007

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