Nmi# Generation Logic; Parity Error Detection - Intel 6300ESB Datasheet

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5—Intel 6300ESB ICH
Figure 8.

NMI# Generation Logic

Pre-latch S_SSE
Pre-latch P_SSE
S_SSE for PCI-X
Pre-latch
USBe_SSE
HubLink Parity Error Detected
D30_P_PER (D30:04h.6)
PCI Parity Error Detected
D30_S_PER (D30:3Eh.0)
South PCI Parity Error Detected
D31_S_PER (D31:04h.6)
5.1.5

Parity Error Detection

The Intel
The Intel
routed to SMI#) based on detecting a parity error. The conceptual logic diagram in
Figure 8
with their respective enable bits, status bits, and the results.
Note: The Intel
device (PERR#) across the P2P bridge.
Note: When NMIs are enabled, and parity error checking on PCI is also enabled, then parity
errors will cause an NMI. Some operating systems will not attempt to recover from this
NMI, since it considers the detection of a PCI error to be a catastrophic event.
November 2007
Order Number: 300641-004US
IOCHK from SERIRQ Logic
Port 61.3
PCI_SERR_STS
(Port 61.2)
OR
D29:F7:06h.14
AND
AND
AND
D30_SDPD (D30:1Eh:8)
D31_DPT (D31:06h.8)
PCI-X PERR_PIN
AND
(D28:3E.0)
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6300ESB ICH may detect and report different parity errors in the system.
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6300ESB ICH may be programmed to cause an NMI (or SMI# when NMI is
details all the parity errors that the Intel
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6300ESB ICH does not escalate a data parity mismatch reported by a PCI
IOCHK_NMI_STS
(Port 61.6)
AND
SERR_NMI_STS
(Port 61.7)
AND
PUSERR_NMI
TCONMI_STS
D30_PDPD
(D30:06h:8)
OR
Port 70:7
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6300ESB ICH may detect, along
To NMI#
OR
AND
Output and
Gating Logic
A9644-01
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Intel 6300ESB I/O Controller Hub
DS
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