Boot Interrupt - Intel 6300ESB Datasheet

5.7.3

Boot Interrupt

The Intel
interrupt inputs together to generate a single interrupt through PIC. This is necessary
for systems that do not support the APIC, and for boot. The generated interrupt is
routed to IRQ 9.
This interrupt is generated when the following conditions met:
•
Boot interrupt is enabled in configuration register.
•
Any of PXIRQ[3:0] or internal interrupt source is asserted.
•
Boot interrupts are not MASKed in redirection table. (Refer to Bit 16 in the
Redirection Table)
•
IRQ9 of PIC is enabled with bit 6 set to 0 of the ETR1- Extended Features Register,
D:31:F0:offset F4h,bit 6 or PIRQG# is assigned to an enabled IRQx of the PIC with
ETR1 bit 6 set to 1. See
Register (LPC I/F—D31:F0)"
To support this function, all internal interrupt sources to APIC1 are level trigger, active
low signals immediately after reset.
®
Intel 6300ESB I/O Controller Hub
DS
122
®
6300ESB ICH's APIC1 contains a capability to logically OR several of its
Section 8.1.37, "Offset F4: ETR1—PCI-X Extended Features
for more information.
®
Intel 6300ESB ICH—5
November 2007
Order Number: 300641-004US