11.1.27 Offset 70 - 73H: Intel Specific Usb Ehci Smi - Intel 6300ESB Datasheet

®
11—Intel 6300ESB ICH
Table 404. Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status
(Sheet 2 of 2)
29
Device:
6C-6Fh
Offset:
00000000h
Default Value:
Bits Name
SMI on Host System
4
Error Enable
SMI on Frame List
3
Rollover Enable
SMI on Port Change
2
Enable
1 SMI on USB Error Enable
SMI on USB Complete
0
Enable

11.1.27 Offset 70 - 73h: Intel Specific USB EHCI SMI

Note: This register provides a mechanism for BIOS to provide USB EHCI related bug fixes and
workarounds. Writing a '1' to that bit location clears bits that are marked as Read/
Write-Clear
(R/WC). Software should clear all SMI status bits prior to setting the global SMI enable
bit and individual SMI enable bit to prevent spurious SMI when returning from a
powerdown.
Table 405. Offset 70 - 73h: Intel Specific USB EHCI SMI (Sheet 1 of 2)
29
Device:
70-73h
Offset:
00000000h
Default Value:
Bits Name
31:2
Reserved
8
27:2
Reserved
6
25:2
SMI on PortOwner
2
21 SMI on PMCSR
20 SMI on Async
November 2007
Order Number: 300641-004US
Attribute:
Power Well:
Description
When this bit is a '1' and the SMI on Host System Error is a
'1', the host controller will issue an SMI.
When this bit is a '1' and the SMI on Frame List Rollover bit is
a '1', the host controller will issue an SMI.
When this bit is a '1' and the SMI on Port Change Detect bit is
a '1', the host controller will issue an SMI.
When this bit is a '1' and the SMI on USB Error bit is a '1', the
host controller will issue an SMI immediately.
When this bit is a '1' and the SMI on USB Complete bit is a '1',
the host controller will issue an SMI immediately.
Attribute:
Power Well:
Description
Reserved. Hardwired to 00h.
Reserved.
Bits 27:22 correspond to the Port Owner bits for ports 0 (22)
through 3 (25). These bits are set to '1' whenever the
associated Port Owner bits transition from '0'->'1' or '1'->'0'.
Software clears these bits by writing a '1'.
This bit is set to '1' whenever software modifies the Power
State bits in the Power Management Control/Status (PMCSR)
register.
This bit is set to '1' whenever the Async Schedule Enable bit
transitions from '1'->'0' or '0'->'1'
7
Function:
Read/Write
32-bit
Size:
Suspend
7
Function:
Read/Write
32-bit
Size:
Suspend
Intel
Access
R/W
R/W
R/W
R/W
R/W
Access
RO
R/WC
R/WC
R/WC
R/WC
®
6300ESB I/O Controller Hub
DS
501