Ac-Link Powerdown Timing; Ac-Link Low Power Mode - Intel 6300ESB Datasheet

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5—Intel 6300ESB ICH
5.20.3

AC-Link Low Power Mode

The AC-link signals may be placed in a low-power mode. When the AC'97 Powerdown
Register (26h), is programmed to the appropriate value, both BIT_CLK and AC_SDIN
will be brought to, and held at a logic low voltage level.
Figure 26. AC-Link Powerdown Timing
BIT_CLK and AC_SDIN transition low immediately, within the maximum specified time,
after a write to the Powerdown Register (26h) with PR4 enabled. When the AC'97
controller driver is at the point where it is ready to program the AC-link into its low-
power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output
frame. At this point in time it is assumed that all sources of audio input have been
neutralized.
The AC'97 controller also drives AC_SYNC, and SDOUT low after programming AC'97 to
this low power, halted mode.
Once the codec has been instructed to halt BIT_CLK, a special wake up protocol must
be used to bring the AC-link to the active mode since normal output and input frames
cannot be communicated in the absence of BIT_CLK. Once in a low-power mode, the
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Intel 6300ESB ICH provides three methods for waking up the AC-link; external wake
event, cold reset and warm reset.
Note: Before entering any low-power mode where the link interface to the codec is expected
to be powered down while the rest of the system is awake, the software must set the
"Shut Off" bit in the control register to ensure that the Intel
does not drive the output pins of the link.
5.20.3.1 External Wake Event
Codecs may signal the controller to wake the AC-link, and wake the system using
AC_SDIN.
November 2007
Order Number: 300641-004US
S Y N C
B IT _ C L K
s lo t 1 2
S D O U T
p re v . fr a m e
s lo t 1 2
S D IN
p re v . fr a m e
N o te :
B IT _ C L K n o t to s c a le
W rite to D a ta
T A G
0 x 2 0 P R 4
T A G
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6300ESB ICH controller
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Intel 6300ESB I/O Controller Hub
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