Intel 6300ESB Datasheet page 4

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USB
— Includes one EHCI USB2 host
controllers, a total of four ports (shared
with the UHCI ports)
— Two UHCI Host Controllers for a total of
four ports (shared with EHCI ports)
— New: supports a USB 2.0 High-speed
Debug Port
— Supports wake-up from sleeping states
S1-S4
— Supports legacy Keyboard/Mouse
software with USB-based keyboard and
mouse
•
AC'97 Link for Audio and Telephony
CODECs
— New: Third AC_SDATA_IN Line for three
codec support
— AC'97 2.2 compliant
— New: Independent bus master logic for
8 channels (PCM In/Out, Mic 1 Input,
Mic 2 Input, Modem In/Out, S/PDIF
Out)
— Separate independent PCI functions for
Audio and Modem
— Support for up four to six channels of
PCM audio output (full AC3 decode)
— Support for 20-bit sample
— Support for ACPI device states - D0 and
D3
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Interrupt Controller
— Supports up to 12 PCI interrupt pins;
four are not shared
— Two cascaded 82C59 with 15 interrupts
— Supports PCI scheme for delivering
interrupts as write cycles (MSI)
— Integrated I/O APIC capability with 24
interrupts
— Supports Serial Interrupt Protocol
— Supports Front-Side Message Interrupt
Delivery
•
New: Multimedia Timers based on 82C54
— Includes three timer comparators
— System timer, Refresh request, Speaker
tone output
— One-shot and periodic interrupts
supported
•
New: Watchdog Timer
— Two-Stage Watchdog with independent
count values for each stage
— First stage generates an INT or SMI
— Second stage drives external pin active
until cleared by a system reset or power
cycle
— Configuration option for write-once
enabling (count values can still change)
— Configurable granularity from 1µs to 10
min
®
Intel 6300ESB I/O Controller Hub
DS
4
•
SMBus
— Flexible SMBus/SMLink architecture to
optimize for ASF and eliminate board
requirements of SMBus 2.0 compliance
— Supports SMBus 2.0 Specification
— Host interface allows CPU to
communicate via SMBus
— Slave interface allows an external
Microcontroller to access system
resources
— Compatible with most 2-wire
components that are also I
compatible
•
New: Integrated 16550 compatible UARTs
— Enable/disable per UARTs
— Serial interrupts
— Can disable when external SIO used
•
New: Port 60/64 Emulation
— Programmable interrupt generation on
writes
— Positive decode to Port 60/64 emulation
registers
•
GPIO
— Four GPOs capable of directly driving
LEDs
— Two GPOs maintain state during and
after reset
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1.5 V operation with 3.3 V I/O. 5 V
tolerance on many buffers, including IDE.
•
Package 37.5 x 37.5 mm 689 BGA
•
Process P859.6
Order Number: 300641-004US
®
Intel 6300ESB ICH—
2
C
November 2007