Glob_Sta-Global Status Register - Intel 6300ESB Datasheet

Table 492. GLOB_CNT—Global Control Register (Sheet 2 of 2)
31
Device:
NABMBAR + 2Ch
I/O Address:
00000000h
Default Value:
No
Lockable:
Bits Name
2 AC'97 Warm Reset
1 AC'97 Cold Reset#
GPI Interrupt Enable
0
(GIE)
13.2.9 GLOB_STA—Global Status Register
Note: Reads across dWord boundaries are not supported.
®
Intel 6300ESB I/O Controller Hub
DS
574
Attribute:
Power Well:
Description
0 = Normal operation.
1 = Writing a '1' to this bit causes a warm reset to occur on
the AC-link. The warm reset will awaken a suspended
codec without clearing its internal registers. When
software attempts to perform a warm reset while bit_clk
is running, the write will be ignored and the bit will not
change. This bit is self-clearing; it remains set until the
reset completes and bit_clk is seen on the ACLink, after
which it clears itself.
0 = Writing a '0' to this bit causes a cold reset to occur
throughout the AC'97 circuitry. All data in the controller
and the codec will be lost. Software must clear this bit no
sooner than the minimum number of ms have elapsed.
1 = This bit defaults to '0' and hence, after reset, the driver
needs to set this bit to a '1'. The value of this bit is
retained after suspends; hence, when this bit is set to a
'1' prior to suspending, a cold reset is not generated
automatically upon resuming.
NOTE: This bit is in the Core well.
This bit controls whether the change in status of any GPI
causes an interrupt.
0 = Bit '0' of the Global Status Register is set, but no
interrupt is generated.
1 = The change on value of a GPI causes an interrupt and
sets bit '0' of the Global Status Register.
5
Function:
Read/Write
32-bit
Size:
Core
Order Number: 300641-004US
®
Intel 6300ESB ICH—13
Access
R/W
(special)
R/W
R/W
November 2007