X_Bdbar-Buffer Descriptor List Base Address Register; X_Civ-Current Index Value Register - Intel 6300ESB Datasheet

®
14—Intel 6300ESB ICH
14.2.1 x_BDBAR—Buffer Descriptor List Base Address
Register
Note: Software may read the register at offset 00h by performing a single 32-bit read from
address offset 00h. Reads across dWord boundaries are not supported.
Table 518. x_BDBAR—Buffer Descriptor List Base Address Register
29
Device:
MBAR + 00h (MIBDBAR),
I/O Address:
MBAR + 10h (MOBDBAR)
00000000h
Default Value:
No
Lockable:
Bits Name
Buffer Descriptor List
31:3
Base Address[31:3]
2:0
14.2.2 x_CIV—Current Index Value Register
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single 32-bit read from address offset 04h. Software may also read this
register individually by doing a single 8-bit read to offset 04h. Reads across dWord
boundaries are not supported.
Table 519. x_CIV—Current Index Value Register
29
Device:
MBAR + 04h (MICIV),
I/O Address:
MBAR + 14h (MOCIV)
00h
Default Value:
No
Lockable:
Bits Name
7:5
Current Index Value
4:0
[4:0]
November 2007
Order Number: 300641-004US
Attribute:
Power Well:
Description
These bits represent address bits 31:3. The entries should be
aligned on 8-byte boundaries.
Hardwired to '0'.
Attribute:
Power Well:
Description
Hardwired to '0'.
These bits represent which buffer descriptor within the list of
16 descriptors is being processed currently. As each
descriptor is processed, this value is incremented.
5
Function:
Read/Write
32-bit
Size:
Core
5
Function:
Read-Only
8-bit
Size:
Core
Intel
Access
R/W
Access
RO
®
6300ESB I/O Controller Hub
DS
595