Offset C4H, C6H, C8H, Cah: Mon[N]_Trp_Rng-I/O Monitor [4:7] Trap Range Register For Devices 4-7 (Pm-D31:F0); Offset Cch: Mon_Trp_Msk-I/O Monitor Trap Range Mask Register For Devices - Intel 6300ESB Datasheet

®
8—Intel 6300ESB ICH
to the intended target and an SMI# will be generated (this is the same functionality as
®
the Intel
6300ESB ICH and the intended target is on LPC, an SMI# will be generated but the
cycle will only be forwarded to the intended target when forwarding to LPC is enabled
through the TRP_FWD_EN register settings.
Table 278. Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7] Trap
Range
Register for Devices 4-7 (PM—D31:F0)
31
Device:
C4h, C6h, C8h, CAh
Offset:
0000h
Default Value:
No
Lockable:
Bits Name
15:0 MON[n]_TRAP_BASE
8.8.1.8 Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask
Register
for Devices 4-7 (PM—D31:F0)
Note: Usage: Legacy Only.
Table 279. Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register
for Devices 4-7 (PM—D31:F0)
31
Device:
CCh
Offset:
00h
Default Value:
No
Lockable:
Bits Name
15:1
MON7_MASK
2
11:8 MON6_MASK
7:4 MON5_MASK
3:0 MON4_MASK
November 2007
Order Number: 300641-004US
6300ESB ICH component). When the cycle is to be claimed by the Intel
Base I/O locations that MON[n] traps (where n = 4, 5, 6 or
7). The range may be mapped anywhere in the CPU I/O space
(0-64K).
Any access to the range will generate an SMI# when enabled
by the associated DEV[n]_TRAP_EN bit in the MON_SMI
register (PMBASE +40h).
Selects low 4-bit mask for the I/O locations that MON7 will
trap. Similar to MON4_MASK.
Selects low 4-bit mask for the I/O locations that MON6 will
trap. Similar to MON4_MASK.
Selects low 4-bit mask for the I/O locations that MON5 will
trap. Similar to MON4_MASK.
Selects low 4-bit mask for the I/O locations that MON7 will
trap. When a mask bit is set to a 1, the corresponding bit in
the base I/O selection will not be decoded.
For example, if MON4_TRAP_BASE = 1230h, and MON4_MSK
®
= 0100b, the Intel
1234h for Monitor 4.
0
Function:
Read/Write
Attribute:
16-bit
Size:
Core
Power Well:
Description
0
Function:
Read/Write
Attribute:
16-bit
Size:
Core
Power Well:
Description
6300ESB ICH will decode 1230h and
®
Access
R/W
Access
R/W
R/W
R/W
R/W
®
Intel 6300ESB I/O Controller Hub
DS
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