Configuring The Layer 2 Circuit Cell-Relay Cell Maximum Overview; Class-Based Cell Bundling - Juniper ACX1000 Configuration Manual

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Configuring the Layer 2 Circuit Cell-Relay Cell Maximum Overview

Class-Based Cell Bundling

Copyright © 2017, Juniper Networks, Inc.
When the router detects that the allotted time interval has expired, the router forwards
the MPLS packet even if it contains fewer than the specified maximum number of
aggregated cells per packet.
Configuring the Layer 2 Circuit Cell-Relay Cell Maximum Overview on page 189
cell-bundle-timeout
By default, each frame contains one cell. For ATM interfaces with Layer 2 circuit cell-relay
transport mode configured, you can configure the maximum number of ATM cells per
frame on the physical or logical interface. To set the maximum number of cells per frame,
include the
cell-bundle-size
cell-bundle-size cells;
You can include this statement at the following hierarchy levels:
[edit interfaces interface-name atm-options]
[edit interfaces interface-name unit logical-unit-number]
[edit logical-systems logical-system-name interfaces interface-name unit
logical-unit-number]
The cell bundle size can be from 1 through 176.
After 125 microseconds, cell bundling times out. This means that after 125 microseconds
if the frame does not contain the configured value, the frame is transmitted anyway.
If you include the cell-bundle-size
hierarchy level, then the configured value becomes the default for all the
atm-options]
logical interface units configured for that physical interface. If you include the
cell-bundle-size statement for a logical interface, the logical interface configuration
overrides the value configured at the physical interface level.
The transmit rates you configure on the routers at each end of the connection must be
the same value.
For Layer 2 circuit trunk mode only, cell bundling is enhanced by a set of CoS and traffic
shaping rules, as follows:
CBR and real-time variable bit rate (RTVBR) cells are not bundled. They are always
sent as single-cell packets.
Cells with the same CLP bits are bundled together. This means all the cells in a bundle
contain the same CLP value.
statement:
statement at the [edit interfaces interface-name
Chapter 6: Configuring ATM Interfaces
189