Automatic Clock Selection Overview; Clock Source Selection Algorithm; Clock Selection And Quality Level - Juniper ACX1000 Configuration Manual

ACX Series Universal Access Router Configuration Guide

Automatic Clock Selection Overview

Clock Source Selection Algorithm

Clock Selection and Quality Level

224
Configuring Hybrid Mode and ESMC Quality Level Mapping on ACX Series
Routers on page 292
Example: Configuring Hybrid Mode and ESMC Quality Level Mapping on page 295
Understanding Timing Defects and Event Management on ACX Series on page 301
Understanding SNMP MIB for Timing on ACX Series on page 303
Global Positioning System (GPS) and the ACX Series Routers on page 306
Integrated Global Navigation Satellite System (GNSS) on ACX500 Series
Routers on page 307
Assisted Partial Timing Support on ACX500 Routers Overview on page 308
Automatic clock selection is the selection of the best quality clock source by the clock
source selection algorithm based on the Ethernet Synchronization Message Channel
(ESMC) Synchronization Status Message (SSM) quality level, the configured quality
level, and the priority.
Clock Source Selection Algorithm on page 224
Clock Selection and Quality Level on page 224
Selection Mode for the Incoming ESMC Quality on page 225
The clock source selection algorithm is triggered by the following events:
Changes in the received ESMC SSM quality level (QL)
Configuration changes. For example, the addition or deletion of a clock source, a change
to the QL mode, and so on.
Signal failure detected on the currently selected source.
When the router is configured with automatic clock selection, the system chooses up to
two best upstream clock sources. The system then uses the clock recovered from one
of the sources to lock the chassis clock. If an upstream clock with acceptable good quality
is not available or if the system is configured in free-run mode, the system uses the internal
oscillator.
Automatic clock selection supports two modes: QL enabled and QL disabled.
QL disabled— In this mode, the best clock is selected based on the configured ESMC
SSM QL. If the QL of the configured clocks are equal, the clock selection is based on
the configured priority. If both the configured QL and priority are equal, one of the
sources is randomly selected. Absence of the
[
edit chassis synchronization
quality-mode-enable
] hierarchy level means that QL is disabled.
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