Figure 14-1 Sourcemeter Status Register Structure - Keithley 6430 Instruction Manual

Figure 14-1
SourceMeter status
register structure
Calibration Summary
Command Warning
(Always Zero)
Operation Complete
Query Error
Device Specific Error
Execution Error
Command Error
User Request
(Always Zero)
Measurement Measurement
Condition
Register
Limit 1 Fail
Low Limit 2 Fail
High Limit 2 Fail HL2F
Low Limit 3 Fail
High Limit 3 Fail HL3F
Limits Pass
Reading Available
Reading Overflow
Buffer Available
Buffer Full
Interlock Asserted
Over Temperature
Over Voltage Protection
Compliance Comp
(Always Zero)
Questionable
Questionable Questionable
Condition Event
Register Register
0 0 &
1 1
&
2 2
&
3 3 &
4 4 &
5 5 &
6 6 &
7 &
7
Cal Cal &
9 9 &
10 10
&
11 &
11
&
12 12
13 13 &
Warn Warn
&
&
15 15
Output Queue
Standard
Event
Standard
Status
Event
Status
Enable
Register Register
OPC & OPC
1 1
&
QYE & QYE
DDE & DDE
EXE & EXE
CME & CME
&
URQ URQ
Power On PON & PON
8 & 8
9 9
&
10 10
&
&
11 11
12 & 12
13 & 13
14 14
&
15 & 15
*ESR? *ESE
*ESE?
Measurement
Event
Event Enable
Register Register
L1 L1 L1
&
LL2F
LL2F LL2F
&
HL2F
HL2F
&
LL3F
LL3F LL3F
&
HL3F HL3F
&
LP LP
& LP
RAV
RAV RAV
&
ROF ROF ROF
&
BAV BAV & BAV
BFL BFL BFL
&
10
10 10
&
INT INT INT
&
OT OT
OT &
OVP OVP OVP
&
Comp Comp
&
15 15 15
&
Event
Enable
Register
0
1
2
3
4
5
6
Logical
7
OR
Cal
9
10
11
12
13
Warn
15
Logical
OR
MSB = Measurement Summary Bit
EAV = Error Available
QSB = Questionable Summary Bit
MAV = Message Available
ESB = Event Summary Bit
RQS/MSS = Request for Service/Master Summary Staus
OSB = Operation Summary Bit
Operation
Condition
Register
Calibrating Cal
1
2
Sweeping
Swp
4
Waiting for Trigger Trig
Arm
Waiting for Arm
Logical
7
OR
8
9
Idle Idle
11
12
13
14
15
Status Structure
Error Queue
Service
Status Request
Byte Enable
Register Register
MSB MSB
&
1 & 1
EAV EAV
&
QSB
QSB
& Logical
MAV OR
&
MAV
ESB ESB
&
RQS/MSS 6
OSB OSB
&
*STB?
*SRE
*SRE?
Master Summary Status (MSS)
Note : RQS bit is in serial poll byte,
MSS bit is in *STB? response.
Operation
Event
Operation
Event Enable
Register
Register
Cal Cal
&
1 1
&
2 & 2
Swp
Swp
&
4 4
&
Trig Trig
&
Arm
Arm
&
7 & 7
8 & 8
9 9
&
Idle Idle
&
11 &
11
12 & 12
13 13
&
14 14
&
15 & 15
14-3
Logical
OR