Effects Of Dynamic Bus Sizing And Operand Misalignment - Motorola MC68020 User Manual

31 LONG-WORD OPERAND (REGISTER)
OP0
D31
MSB
XXX
OP1
Figure 5-17. Misaligned Long-Word Operand Read

5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment

The combination of operand size, operand alignment, and port size determine the number
of bus cycles required to perform a particular memory access. Table 5-6 lists the number
of bus cycles required for different operand sizes to different port sizes with all possible
alignment conditions for read/write cycles.
Operand Size
Instruction
Byte Operand
Word Operand
Long-Word Operand
*
Instruction prefetches are always two words from a long-word boundary
Table 5-6 reveals that bus cycle throughput is significantly affected by port size and
alignment. The MC68020/EC020 system designer and programmer should be aware of
and account for these effects, particularly in time-critical applications.
5-20
OP1 OP2
DATA BUS
LONG-WORD MEMORY
UMB LMB
XXX XXX
OP2 OP3
from Long-Word Port Example
Table 5-6. Memory Alignment and Port Size
Influence on Read/Write Bus Cycles
(Data Port Size = 32 Bits:16 Bits:8 Bits)
00
*
1:2:4
1:1:1
1:1:2
1:2:4
M68020 USER'S MANUAL
0
OP3
D0
MC68020/EC020
LSB SIZ1 SIZ0 A2
OP0 0 0
XXX 1 1
Number of Bus Cycles
A1, A0
01 10
N/A N/A
1:1:1 1:1:1
1:2:2 1:1:2
2:3:4 2:2:4
MEMORY CONTROL
A1 A0 DSACK1 DSACK0
0 1 1 L
1 0 0 L
11
N/A
1:1:1
2:2:2
2:3:4
MOTOROLA
L
L