Vme Subsystem Bus (Vsbbus); Dynamic Ram - Motorola MVME135 User Manual

FUNCTIONAL DESCRIPTION
MC68020, the PMMU provides a logical extension to the program
control and processing abilities of the main processor. It does
this by providing a set of translation, protection, and breakpoint
registers that control operation of the memory management
mechanism. These registers are utilized in a manner similar to the
use of any internal processor register.
4.6 DEBUG MONITOR FIRMWARE
The MVME135bug Debug Monitor firmware package is optionally
available for use with any of the MVME135/136 modules. This
firmware offers 32 debug capability, upload/download, disk
bootstrap commands, a one line assembler/disassembler with full
MC68881 support, as well as a full set of on-board diagnostics.
Refer to the 135bug Diagnostic/Debug Package User's Manual for a
detailed description of its operation.
4.7 VME SUBSYSTEM BUS (VSBbus)
The VME Subsystem Bus (VSBbus is a subset of the VMEbus) is a local
extension bus. It allows a processor board to access additional
memory and I/O over a local bus, removing traffic from the global bus
and improvi ng the total throughput of the system. The VSBbus
interface occupies 64 I/O pins on connector P2 and utilizes the
multiplexing of address and data in order to accommodate full 32-bit
functionality, along with appropriate control signals, within the
64-pin allotment.
On the MVME135/136 modules, VSBbus is implemented through the use of
the MVSB2400. The MVSB2400 is a 132-pin gate array subset of the
VSBbus specification in a PGA package. The MVSB2400 provides most
of the functionality required to support a master VSBbus interface
using one VLSI device and a few external gates, and contains most of
the bus drivers for the VSBbus and all of the address and data
multiplexing circuits. Refer to the MVSB2400 VSBchip User's Manual
for a deta i
1
ed descri pt
i
on of its operat ion. Although the MVSB2400
VSBchip has a slave mode, the MVME135/136 does not support VSBbus
sl ave accesses.
4.8
DYNAMIC RAM
The MVME135/136's dynamic random access memory uses 256K x 1 or 1M x
1 dynamic RAMs surface mounted on a mezzanine board, providing a
total of 1Mb to 4Mb of local DRAM with optional parity.
It
is
accessible from the MC68020, the refresh circuitry, and the VMEbus,
each of which requests and is granted use of the DRAM by an on-board
arbiter.
The on-board DRAM is designed to operate at zero wait cycles at both
16.67 MHz and 20.00 MHz without parity and a bypass board installed
4-7
I