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ESAI/EXTAL
control bit
ETI1
ETO1
ERI1
ERO1
ETI0
ETO0
ERI0
ERO0
6.2.3
Port H Signals and Registers
Each of the five Port H signals (MODA, MODB, MODC, MODD and HREQ) can be configured individually as a GPIO signal. The GPIO
functionality of Port H is controlled by three registers: Port H control register (PCRH), Port H direction register (PRRH) and Port H data
register (PDRH).
6.2.3.1
Port H Control Register (PCRH)
The read/write 24-bit Port H Control Register (PCRH) in conjunction with the Port H Direction Register (PRRH) controls the functionality
of the dedicated GPIO pins. Each of the PH(4:0) bits controls the functionality of the corresponding port pin. See
configurations. Hardware and software reset sets all PCRH bits.
6.2.3.2
Port H Direction Register (PRRH)
The read/write 24-bit Port H Direction Register (PRRH) in conjunction with the Port H Control Register (PCRH) controls the functionality
of the dedicated GPIO pins.
Table 6-3.
Freescale Semiconductor
Table 6-2. ESAI/EXTAL clock bit descriptions
When this bit is set, the EXTAL clock can be used to generate the ESAI_1
transmitter clocks : HCKT_1, SCKT_1 and FST_1.
When this bit is cleared, the Fosc clock can be used to generate the ESAI_1
transmitter clocks : HCKT_1, SCKT_1 and FST_1.
When this bit is set, the EXTAL clock is directed to the HCKT_1 pin.
When this bit is cleared, EXTAL clock is not directed to the HCKT_1 pin
When this bit is set, the EXTAL clock can be used to generate the ESAI_1
receiver clocks : HCKR_1, SCKR_1 and FSR_1.
When this bit is cleared, the Fosc clock can be used to generate the ESAI_1
receiver clocks : HCKR_1, SCKR_1 and FSR_1.
When this bit is set, the EXTAL clock is directed to the HCKR_1 pin.
When this bit is cleared, the EXTAL clock is not directed to the HCKR_1 pin.
When this bit is set, the EXTAL clock can be used to generate the ESAI
transmitter clocks : HCKT, SCKT and FST.
When this bit is cleared, the Fosc clock can be used to generate the ESAI
transmitter clocks : HCKT, SCKT and FST.
When this bit is set, the EXTAL clock is directed to the HCKT pin.
When this bit is cleared, the EXTAL clock is not directed to the HCKT pin.
When this bit is set, the EXTAL clock can be used to generate the ESAI
receiver clocks : HCKR, SCKR and FSR.
When this bit is cleared, the Fosc clock can be used to generate the ESAI
receiver clocks : HCKR, SCKR and FSR.
When this bit is set, the EXTAL clock is directed to the HCKR pin.
When this bit is cleared, the EXTAL clock is not directed to the HCKR pin.
describes the port-pin configurations. Hardware and software reset sets all PRRH bits.
Table 6-3. PCRH and PRRH Bits Functionality
PDH[i]
PH[i]
0
0
0
1
DSP56374 Users Guide, Rev. 1.2
Bit description
Port Pin[i] Function
Disconnected
GPIO input
Programming Model
Table 6-3.
for the port-pin
6-3
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