Table of Contents
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Paragraph
Number
1.1
Introduction ...............................................................................................................................................................1-1
1.2
DSP56300 Core Description .....................................................................................................................................1-2
1.3
DSP56374 Audio Processor Architecture .................................................................................................................1-3
1.4
DSP56300 Core Functional Blocks ...........................................................................................................................1-3
1.4.1
Data ALU ............................................................................................................................................................1-3
1.4.1.1
Data ALU Registers ......................................................................................................................................1-3
1.4.1.2
Multiplier-Accumulator (MAC) ...................................................................................................................1-3
1.4.2
Address Generation Unit (AGU) ........................................................................................................................1-4
1.4.3
Program Control Unit (PCU) ..............................................................................................................................1-4
1.4.4
Internal Buses ......................................................................................................................................................1-4
1.4.5
Direct Memory Access (DMA) ...........................................................................................................................1-5
1.4.6
PLL-based Clock Oscillator ................................................................................................................................1-5
1.4.7
On-Chip Memory ................................................................................................................................................1-5
1.4.8
Off-Chip Memory Expansion .............................................................................................................................1-5
1.4.9
Power Requirements ...........................................................................................................................................1-5
1.5
Peripheral Overview ..................................................................................................................................................1-6
1.5.1
General Purpose Input/Output (GPIO) ...............................................................................................................1-6
1.5.2
Triple Timer (TEC) .............................................................................................................................................1-6
1.5.3
Enhanced Serial Audio Interface (ESAI) ............................................................................................................1-7
1.5.4
Enhanced Serial Audio Interface 1 (ESAI_1) .....................................................................................................1-7
1.5.5
Serial Host Interface (SHI) .................................................................................................................................1-7
1.5.6
Watchdog timer (WDT) ......................................................................................................................................1-7
2.1
Signal Groupings .......................................................................................................................................................2-1
2.2
Power .........................................................................................................................................................................2-1
2.3
Ground .......................................................................................................................................................................2-3
2.4
SCAN ........................................................................................................................................................................2-4
2.5
Clock and PLL ...........................................................................................................................................................2-4
2.6
Interrupt and Mode Control .......................................................................................................................................2-4
2.7
Serial Host Interface ..................................................................................................................................................2-6
2.8
Enhanced Serial Audio Interface ...............................................................................................................................2-8
2.9
Enhanced Serial Audio Interface_1 .........................................................................................................................2-12
2.10
Dedicated GPIO - Port G .........................................................................................................................................2-16
2.11
Timer .......................................................................................................................................................................2-18
2.12
JTAG/OnCE Interface .............................................................................................................................................2-19
3.1
Data and Program Memory Maps .............................................................................................................................3-1
3.1.1
Reserved Memory Spaces ...................................................................................................................................3-5
3.1.2
Bootstrap CODE .................................................................................................................................................3-5
3.1.3
Dynamic Memory Configuration Switching ......................................................................................................3-5
Freescale Semiconductor
Table of Contents
Preface i
Chapter 1
Chapter 2
Chapter 3
DSP56374 Users Guide, Rev. 1.2
Page
Number
TOC-1
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