Pll Output Frequency (Pll Out) - Freescale Semiconductor DSP56374 User Manual

PLL Operation
EXTAL
Predivider
1 to 31
PD[4–0]
Figure 5-3. PLL Loop with One Divider when OD1=0 (FM = 2)
EXTAL
Predivider
1 to 31
PD[4–0]
Figure 5-4. PLL Loop with Two Dividers when OD1=1 (FM = 4)
5.4.3

PLL Output Frequency (PLL Out)

The PLL Output frequency is a function of the VCO frequency as follows:
As described above the Output Divider Factor is 2 or 4 as determined by the OD1 and OD0 bits. Note that since OD0 is not in the closed loop
of the PLL, changes to OD0 do not cause a loss of lock condition. The figures below show how the OD [1-0] bits affect the PLL Output
frequency by dividing the VCO Output.
Output that is VCO Out/2
Ft
5-4
Fref
Phase
Charge Pump
Detector and
Loop Filter
Frequency
Divider
MF[7–0] 1 to 255
Fref
Phase
Charge Pump
Detector and
Loop Filter
Frequency
Divider
MF[7–0] 1 to 255
PLL Out
Figure 5-5 displays how setting OD1 = 0 and OD0 = 1 divides the VCO output to generate a PLL
DSP56374 Users Guide, Rev. 1.2
OD1
VCO Out
0
VCO
1
Divide
by 2
FM
Divide
by 2
NOTE:
5 MHz < Fref < 20 MHz
300 MHz < VCO Out< 600 MHz
OD1
VCO Out
0
VCO
1
Divide
by 2
FM
Divide
by 2
NOTE:
5 MHz < Fref < 20 MHz
300 MHz < VCO Out< 600 MHz
VCO
------------ -
=
OD
Clock
Generator
0 0
PLL Out
1
1
PEN
OD0
Clock
0 0
Generator
PLL Out
1
1
PEN
OD0
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