Appendix A Bootstrap Source Code; Dsp56374 Bootstrap Program - Freescale Semiconductor DSP56374 User Manual

Appendix A
Bootstrap Source Code
A.1

DSP56374 Bootstrap Program

; BOOTSTRAP CODE FOR DSP56374 Rev. 0 silicon -
; (C) Copyright 2003- Freescale Semiconductor, Inc. (formerly Motorola)
;
;
; Revision 0.0 19 Sep 2003 -
; Modified from 56371Boot.asm:
; Operation mode
; MD:MC:MB:MA
; 2: 0 0 1 0: Jump to ROM
; 5: 0 1 0 1: Boot via SPI (slave)
; 6: 0 1 1 0: Boot via I2C with spike filter (slave)
; 7: 0 1 1 1: Boot via I2C w/o spike filter (slave)
; 9: 1 0 0 1: Boot via I2C Serial EEPROM with spike filter (master)
; B: 1 0 1 1: Boot via SPI Serial EEPROM (master)
; C: 1 1 0 0: Boot via GPIO Serial SPI EEPROM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
page 132,55,0,0,0
opt cex,mex,mu
section BOOTSTRAP
XDEF BootStrap
;;
;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;
;;
PROMADDR equ $FF01B0
MA EQU 0
MB EQU 1
MC EQU 2
MD EQU 3
;;
;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;;
;;
ifqROM
STRAP_STARTEQU$ff0000
else
STRAP_STARTEQU$4700
endif
M_OGDB EQU $FFFFFC
OMRSave EQU$102
M_HRX EQU $FFFF94
M_HCSR EQU $FFFF91
M_HCKR EQU $FFFF90
HRNE EQU 17
HI2C EQU 1
HCKFR EQU 4
HFM0 EQU 12
HFM1 EQU 13
Freescale Semiconductor
; Starting PROM address
; OnCE GDB Register
; SHI Receive FIFO
; SHI Control/Status Register
; SHI Clock Control Register
; SHI FIFO Not Empty flag
; SHI I2C Enable Control Bit
; SHI I2C Clock Freeze Control Bit
; SHI I2C Filter Mode Bit 0
; SHI I2C Filter Mode Bit 1
DSP56374 Users Guide, Rev. 1.2
DSP56374 Bootstrap Program
A-1