Freescale Semiconductor DSP56374 User Manual page 256

Index
Receive Data In Slave Mode 15
Slave Mode 14
Start and Stop Events 12
Transmit Data In Master Mode 16
Transmit Data In Slave Mode 15
2
I C Bus Acknowledgment 12
2
I C Mode 1
initializing the timer 2
Inter Integrated Circuit Bus 7, 1
internal buses 4
Internal Exception Priorities
SHI 4
interrupt 4
interrupt and mode control 1, 4, 5
interrupt control 4, 5
Interrupt Service Routine (ISR) 3
Interrupt Vectors
SHI 4
Inverter (INV) bit 22, 24
J
JTAG 19
JTAG/OnCE port 1
L
LA register 4
LC register 4
Locked state, PLL 2
Loop Address register (LA) 4
Loop Counter register (LC) 4
Low-Power Divider (LPD) 6
M
MAC 3
Manual Conventions iii
memory
on-chip 5
MF (Multiplication Factor) 3, 10
mode control 4, 5
modulo adder 4
Multiplication Factor 3, 10
multiplier-accumulator (MAC) 3
O
offset adder 4
OMR register 4
OnCE module 19
on-chip memory 5
operating mode 2
Operating Mode Register (OMR) 4
P
PAB 5
PAG 4
PC register 4
PCU 4
PDB 5
PDC 4
Peripheral I/O Expansion Bus 4
Phase Detector (PD) 2
Phase Locked Loop (PLL). See PLL
PIC 4
PINIT 1
Index-2
PLL 5, 1, 4
clock generator 1
Control (PCTL) register 7
Bit Definitions 8
Division Factor (DF) bit 9
Multiplication Factor (MF) bits 10
PLL Enable (PEN) bit 9
PLL Stop State (PSTP) bit 9
Predivider Factor (PD) bit 8
Control Elements in its circuitry
clock input division 3
frequency multiplication 3
control mechanisms 1
charge pump loop filter 2
frequency predivider 2
phase detector 2
Division Factor 3
PCTL Multiplication Factor 3
PCTL Predivider Factor (PDF) bits 3
Port A 1
Port B 1
Port C 1, 8, 12, 1
Port D 16, 1, 3
power 1
Prescaler Clock Enable (PCE) bit 21
prescaler counter 18
Prescaler Counter Value (PC) bits 20
Prescaler Preload Value (PL) bits 20
Prescaler Source (PS) bits 20
Program Address Bus (PAB) 5
Program Address Generator (PAG) 4
Program Control Unit (PCU) 4
Program Counter register (PC) 4
Program Data Bus (PDB) 5
Program Decode Controller (PDC) 4
Program Interrupt Controller (PIC) 4
Program Memory Expansion Bus 4
Programming Model
SHI—DSP Side 3
SHI—Host Side 3
programming model
timer 18
R
RESET 5
reverse-carry adder 4
S
SC register 4
Serial Host Interface 1, 6
Serial Host Interface (SHI) 7, 1
Serial Host Interface—See Section 5
Serial Peripheral Interface Bus 7, 1
setting timer operating mode 2
SHI 7, 1, 6, 1
Block Diagram 2
Clock Control Register—DSP Side 5
Clock Generator 2
Control/Status Register—DSP Side 7
Data Size 8
Exception Priorities 4
HCKR
DSP56374 Users Guide, Rev. 1.2
Freescale Semiconductor