Table of Contents
Advertisement
SHI Programming Considerations
•
SS/HA2 is the HA2 slave device address input.
•
HREQ is the Host Request input.
2
In the I
C master mode, a data transfer session is always initiated by the DSP by writing to the HTX register when HIDLE is set. This condition
ensures that the data byte written to HTX is interpreted as being a slave address byte. This data byte must specify the slave device address to
be selected and the requested data transfer direction.
The slave address byte should be located in the high portion of the data word, whereas the middle and
low portions are ignored. Only one byte (the slave address byte) is shifted out, independent of the
word length defined by the HM[1:0] bits.
In order for the DSP to initiate a data transfer the following actions are to be performed:
•
The DSP tests the HIDLE status bit.
•
If the HIDLE status bit is set, the DSP writes the slave device address and the R/W bit to the most significant byte of HTX.
•
The SHI generates a start event.
•
The SHI transmits one byte only, internally samples the R/W direction bit (last bit) and accordingly initiates a receive or transmit
session.
•
The SHI inspects the SDA level at the ninth clock pulse to determine the ACK value. If acknowledged (ACK = 0), it starts its receive
or transmit session according to the sampled R/W value. If not acknowledged (ACK = 1), the HBER status bit in HCSR is set, which
causes an SHI Bus Error interrupt request if HBIE is set, and a stop event is generated.
The HREQ input pin is ignored by the I
HREQ indicates that the external slave device is ready for the next data transfer. As a result, the I
full data word transfer. HREQ is de-asserted by the external slave device at the first clock pulse of the next data transfer. When de-asserted,
HREQ prevents the clock generation of the next data word transfer until it is asserted again. Connecting the HREQ line between two
SHI-equipped DSPs, one operating as an I
7.7.4.1
Receive Data in I
A receive session is initiated if the R/W direction bit of the transmitted slave device address byte is set. Following a receive initiation, data in
the SDA line is shifted into IOSR MSB first. Following each received byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via the
SDA line if the HIDLE control bit is cleared. Data is acknowledged byte-wise, as required by the I
HRX FIFO when the complete word (according to HM[1:0]) is filled into IOSR. It is the responsibility of the programmer to select the correct
2
number of bytes in an I
C frame so that they fit in a complete number of words. For this purpose, the slave device address byte does not count
as part of the data; therefore, it is treated separately.
2
If the I
C slave transmitter is acknowledged, it should transmit the next data byte. In order to terminate the receive session, the programmer
should set the HIDLE bit at the last required data word. As a result, the last byte of the next received data word is not acknowledged, the slave
transmitter releases the SDA line, and the SHI generates the stop event and terminates the session.
In a receive session, only the receive path is enabled and the HTX-to-IOSR transfers are inhibited. If the HRNE status bit is set, the HRX
FIFO contains valid data, which may be read by the DSP with either DSP instructions or DMA transfers. When the HRX FIFO is full, the SHI
suspends the serial clock just before acknowledge. In this case, the clock is reactivated when the FIFO is read (the SHI gives an ACK = 0 and
proceeds receiving).
7.7.4.2
Transmit Data In I
A transmit session is initiated if the R/W direction bit of the transmitted slave device address byte is cleared. Following a transmit initiation,
the IOSR is loaded from HTX (assuming HTX is not empty) and its contents are shifted out, MSB-first, on the SDA line. Following each
transmitted byte, the SHI controller samples the SDA line at the ninth clock pulse and inspects the ACK status. If the transmitted byte was
acknowledged (ACK=0), the SHI controller continues transmitting the next byte. However, if it was not acknowledged (ACK=1), the HBER
status bit is set to inform the DSP side that a bus error (or overrun, or any other exception in the slave device) has occurred. Consequently, the
2
I
C master device generates a stop event and terminates the session.
HTX contents are transferred to the IOSR when the complete word (according to HM[1:0]) has been shifted out. It is, therefore, the
responsibility of the programmer to select the right number of bytes in an I
that for this purpose, the slave device address byte does not count as part of the data.
In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited. When the HTX transfers its valid
data word to the IOSR, the HTDE status bit is set and the DSP may write a new data word to HTX with either DSP instructions or DMA
transfers. If both IOSR and HTX are empty, the SHI suspends the serial clock until new data is written into HTX (when the SHI proceeds with
the transmit session) or HIDLE is set (the SHI reactivates the clock to generate the stop event and terminate the transmit session).
7-16
NOTE
2
C master device if HRQE[1:0] are cleared, and it is considered if either of them is set. When asserted,
2
C master device and the other as an I
2
C Master Mode
2
C Master Mode
DSP56374 Users Guide, Rev. 1.2
2
C master device sends clock pulses for the
2
C slave device, enables full hardware handshaking.
2
C bus protocol, and is transferred to the
2
C frame so that they fit in a complete number of words. Remember
Freescale Semiconductor
Advertisement
Table of Contents
