Tcr Esai Transmit 2 Enable (Te2) - Bit 2 - Freescale Semiconductor DSP56374 User Manual

ESAI Programming Model
11
TSWS1 TSWS0 TMOD1 TMOD0
23
TLIE
Hardware and software reset clear all the bits in the TCR register. The ESAI TCR register is located at x:$FFFFB5. The ESAI_1 TCR register
is located at y:$FFFF95.
The TCR bits are described in the following paragraphs.
8.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0
TE0 enables the transfer of data from TX0 to the transmit shift register #0. When TE0 is set and a frame sync is detected, the transmit #0
portion of the ESAI is enabled for that frame. When TE0 is cleared, the transmitter #0 is disabled after completing transmission of data
currently in the ESAI transmit shift register. The SDO0 output is tri-stated, and any data present in TX0 is not transmitted, i.e., data can be
written to TX0 with TE0 cleared, but data is not transferred to the transmit shift register #0.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit
disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE0 and setting it again disables the transmitter #0 after completing transmission of the current
data word until the beginning of the next frame. During that time period, the SDO0 pin remains in the high-impedance state.The on-demand
mode transmit enable sequence can be the same as the normal mode, or TE0 can be left enabled.
8.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1
TE1 enables the transfer of data from TX1 to the transmit shift register #1. When TE1 is set and a frame sync is detected, the transmit #1
portion of the ESAI is enabled for that frame. When TE1 is cleared, the transmitter #1 is disabled after completing transmission of data
currently in the ESAI transmit shift register. The SDO1 output is tri-stated, and any data present in TX1 is not transmitted, i.e., data can be
written to TX1 with TE1 cleared, but data is not transferred to the transmit shift register #1.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit
disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE1 and setting it again disables the transmitter #1 after completing transmission of the current
data word until the beginning of the next frame. During that time period, the SDO1 pin remains in the high-impedance state. The on-demand
mode transmit enable sequence can be the same as the normal mode, or TE1 can be left enabled.
8.3.2.3

TCR ESAI Transmit 2 Enable (TE2) - Bit 2

TE2 enables the transfer of data from TX2 to the transmit shift register #2. When TE2 is set and a frame sync is detected, the transmit #2
portion of the ESAI is enabled for that frame. When TE2 is cleared, the transmitter #2 is disabled after completing transmission of data
currently in the ESAI transmit shift register. Data can be written to TX2 when TE2 is cleared but the data is not transferred to the transmit
shift register #2.
The SDO2/SDI3 pin is the data input pin for RX3 if TE2 is cleared and RE3 in the RCR register is set. If both RE3 and TE2 are cleared, the
transmitter and receiver are disabled, and the pin is tri-stated. Both RE3 and TE2 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit
disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE2 and setting it again disables the transmitter #2 after completing transmission of the current
data word until the beginning of the next frame. During that time period, the SDO2/SDI3 pin remains in the high-impedance state. The
on-demand mode transmit enable sequence can be the same as the normal mode, or TE2 can be left enabled.
8-10
10 9 8 7
TWA
22 21 20 19
TIE TEDIE TEIE TPR
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-5. TCR Register
DSP56374 Users Guide, Rev. 1.2
6 5 4 3
TSHFD TE5 TE4 TE3
18 17 16 15
PADC TFSR TFSL
2 1 0
TE2 TE1 TE0
14 13 12
TSWS4 TSWS3 TSWS2
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