Freescale Semiconductor SC140 DSP Core Reference Manual

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SC140 DSP Core

Reference Manual

Revision 4.1, September 2005

This document contains information on a new product.

Specifications and information herein are subject to

change without notice.

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Page 1 SC140 DSP Core Reference Manual Revision 4.1, September 2005 This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc. 2005, All rights...
Page 2 LICENSOR is defined as Freescale Semiconductor, Inc. LICENSOR reserves the right to make changes without further notice to any products included and covered hereby. LICENSOR makes no warranty, representation or guarantee regarding the suitability of its products for any particular...
Page 3: Table Of Contents
DALU Arithmetic and Rounding ........2-17 SC140 DSP Core Reference Manual...
Page 4 Instruction Word Transfers ........2-62 2.4.1.6 Memory Access Behavior in Big/Little Endian Modes ....2-64 SC140 DSP Core Reference Manual...
Page 5 Real-Time Data Transfer ........4-34 SC140 DSP Core Reference Manual...
Page 6 Trace Buffer Register (TB_BUFF)....... . . 4-69 SC140 DSP Core Reference Manual...
Page 7 Shadow Stack Pointer Registers ........5-35 SC140 DSP Core Reference Manual...
Page 8 Immediate Data Transfer to ISAP registers ......6-62 viii SC140 DSP Core Reference Manual...
Page 9 Delayed COF Rules ..........7-19 SC140 DSP Core Reference Manual...
Page 10 Encoding Notation ..........A-6 SC140 DSP Core Reference Manual...
Page 11 Using the StarCore Registry ......... B-1 SC140 DSP Core Reference Manual...
Page 12 SC140 DSP Core Reference Manual...
Page 13: List Of Figures
Typical Debugging System........4-10 SC140 DSP Core Reference Manual...
Page 14 Core to Single ISAP Connection Schematic......6-58 Core to Multiple ISAP Connection Schematic ......6-59 SC140 DSP Core Reference Manual...
Page 15: List Of Tables
JTAG Interface Signal Descriptions ........4-2 SC140 DSP Core Reference Manual...
Page 16 Processing State Transitions ........5-43 SC140 DSP Core Reference Manual...
Page 17 SCID Assignments ..........B-2 SC140 DSP Core Reference Manual...
Page 18 SC140 DSP Core Reference Manual...
Page 19 Duplicate PC Destinations ......... 7-9 Duplicate Address Pointer Register Destinations ......7-9 SC140 DSP Core Reference Manual...
Page 20 SR Write to SR Status Bit Use ........7-25 SC140 DSP Core Reference Manual...
Page 21 7-80 Memory Write to Stack in a Return Delay Slot ......7-42 SC140 DSP Core Reference Manual...
Page 22 COF Destination to Loop Delay Slots ....... 7-60 xxii SC140 DSP Core Reference Manual...
Page 23: Audience
• Appendix A, “SC140 DSP Core Instruction Set,” references the SC140 instruction set. • Appendix B, “StarCore Registry,” shows how to access the core version SC140 DSP Core Reference Manual xxiii...
Page 24: Abbreviations
EOnCE status register ETRSMT EOnCE transmit register Extension portion of a data register Fetch counter FIFO First-in first-out Fast Fourier transform High portion of a data register Interrupt priority level ISAP Instruction Set Accelerator Plug-in xxiv SC140 DSP Core Reference Manual...
Page 25 Normal mode stack pointer Operating system Program address bus Program address generator Program counter register Program control unit Program data bus Program dispatch unit Programmable interrupt controller Phase locked loop PSEQ Program sequencer unit AGU address register n SC140 DSP Core Reference Manual...
Page 26: Revision History
Data memory data bus A XDBB Data memory data bus B Revision History Table 2. Revision History Revision Date Description 31 Aug, 2004 Fourth release of SC140 20 Sep, 2005 Misc. corrections (restored missing IADDNC.W instruction) xxvi SC140 DSP Core Reference Manual...
Page 27: Introduction
Third generation wireless handset systems with wideband data services • Wireless and wireline base stations as well as the corresponding infrastructure • Speech coding, synthesis, and voice recognition • Wireless internet and multimedia • Network and data communication SC140 DSP Core Reference Manual...
Page 28: Architectural Differentiation
— 32-bit address space for both program and data (byte-addressable). — Unified data and program memory space. — Decoupled external memory timing with independent clock. • Core Organization and Design — Supports flexible system-on-a-chip (SoC) configurations. — Portable across fabrication lines and foundries. SC140 DSP Core Reference Manual...
Page 29: Core Architecture Features
Position independent code utilizing change-of-flow instructions that are relative to the program counter (PC) • Enhanced on-chip emulation (EOnCE) module with real-time debug capabilities • Low power wait standby mode • Very low power complementary metal-oxide semiconductor (CMOS) design • Fully static logic SC140 DSP Core Reference Manual...
Page 30: Typical System-On-Chip Configuration
— Direct memory access (DMA) controller — L2 Cache controller for either data or program — Chip-level Interrupt control unit — On-chip Level 2 (M2) memory expansion modules — Other processor cores with their supporting platforms SC140 DSP Core Reference Manual...
Page 31: Variable Length Execution Set (Vles) Software Model
In order to execute signal processing kernels, a set of SC140 instructions can be grouped to be executed in parallel. The PSEQ performs this automatically with up to four DALU instructions and two AGU instructions executed at the same time. SC140 DSP Core Reference Manual...
Page 32 Core Architecture Features SC140 DSP Core Reference Manual...
Page 33: Core Architecture
Program data and address buses (PDB and PAB) for carrying program words from the memory to the core. • Special buses to support tightly coupled external user-definable instruction set accelerators. A block diagram of the SC140 core is shown in Figure 2-3. SC140 DSP Core Reference Manual...
Page 34: Data Arithmetic Logic Unit (Dalu)
MOVE.W or MOVE.F loads or stores integer or fractional words (16-bit). • MOVE.2W, MOVE.2F or MOVE.L loads or stores two integers, two fractions and long words respectively (32-bit). • MOVE.4W or MOVE.4F loads or stores four integers or four fractions, respectively (64-bit). SC140 DSP Core Reference Manual...
Page 35: Data Register File
The AGU contains address registers and performs address calculations using integer arithmetic necessary to address data operands in memory. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel with other core resources to minimize address generation overhead. SC140 DSP Core Reference Manual...
Page 36: Stack Pointer Registers
Only a single bit mask instruction is allowed in any single execution set since only one execution unit exists for these instructions. A subgroup of the bit mask instructions (BMTSET) provides hardware support of semaphoring, providing one instruction for read-modify-write. SC140 DSP Core Reference Manual...
Page 37: Program Sequencer Unit (Pseq)
However, it may issue stalls due to its specific implementation. Refer to Section 2.4, “Memory Interface,” for further details. Both internal and external memory configurations are specific to each member of the SC140 family. SC140 DSP Core Reference Manual...
Page 38: Dalu
XDBA and XDBB buses in a single cycle Figure 2-2 shows the architecture of the DALU. Memory Data Bus 1 (XDBA) Memory Data Bus 2 (XDBB) (8) Shifter/Limiters Data Registers D0–D15 Figure 2-2. DALU Architecture SC140 DSP Core Reference Manual...
Page 39: Dalu Programming Model
D3.e D3.h D5.e D5.h D5.l D6.e D6.h D6.l D7.e D7.h D7.l D8.e D8.h D8.l D9.e D9.h D9.l D10.e D10.h D10.l D11.e D11.h D11.l D12.e D12.h D12.l D13.e D13.h D13.l D14.e D14.h D14.l D15.e D15.h D15.l SC140 DSP Core Reference Manual...
Page 40: Data Registers (D0-D15)
(Dn.1[7:0]) is written with the byte operand. The following eight bits of the LP (Dn.1[15:8]), the high portion, and the EXT are either zero-extended or sign-extended from the LP lower byte. The limit tag bit (Ln) is cleared. SC140 DSP Core Reference Manual...
Page 41: Write To Data Registers
XDBA or XDBB. Table 2-4 summarizes the various data widths for data moves from/to the data register file. SC140 DSP Core Reference Manual...
Page 42: Multiply-Accumulate (Mac) Unit
Add without changing the carry bit in the SR Add and round Arithmetic shift left by one bit Arithmetic shift right by one bit Clear CMPEQ Compare for equal CMPGT Compare for greater than CMPHI Compare for higher (unsigned) 2-10 SC140 DSP Core Reference Manual...
Page 43 Transfer minimum signed value Multiply signed fractions MPYR Multiply signed fractions and round MPYSU Multiply signed fraction and unsigned fraction MPYUS Multiply unsigned fraction and signed fraction MPYUU Multiply unsigned fraction and unsigned fraction SC140 DSP Core Reference Manual 2-11...
Page 44: Bit-Field Unit (Bfu)
• Sign or zero extension operations Table 2-6 lists the instructions which are executed in the BFU. A more detailed description of each instruction is given in Appendix A, “SC140 DSP Core Instruction Set.” 2-12 SC140 DSP Core Reference Manual...
Page 45: Data Shifter/Limiter
Each consists of a shifter for scaling followed by a limiter. Note that arithmetic saturation from DALU operations is a different function. Saturation occurs in the DALU before data is written to a destination register. SC140 DSP Core Reference Manual 2-13...
Page 46: Scaling
If the bits are not all zeros or all ones, the extension is effectively in use and the Ln bit will be set. The Ln bit is cleared as data is written to a DALU register if the defining bits below are all zeros or all ones. 2-14 SC140 DSP Core Reference Manual...
Page 47 If the arithmetic saturation mode is set in the SR, scaling is not considered in the calculation of the Ln bit. An example of limiting is provided in Table 2-9. SC140 DSP Core Reference Manual 2-15...
Page 48: Scaling And Arithmetic Saturation Mode Interactions
Cleared no scaling no scaling Up/down Calculated, Calculated, Cleared with scaling with scaling Cleared Calculated, Cleared no scaling Up/down Cleared Calculated, Cleared no scaling Note: Limiting will occur if the Ln bit is set. 2-16 SC140 DSP Core Reference Manual...
Page 49: Dalu Arithmetic And Rounding
(LSB) of the value. Figure 2-3 shows the location of the decimal point (binary point) bit weighting and operand alignment for different fractional and integer representations supported on the SC140 architecture. SC140 DSP Core Reference Manual 2-17...
Page 50: Data Formats
, and the most positive long word is $7FFF FFFF or 1.0–2 –31 If the extension bits are in use, the most positive number is 256 – 2 represented by $7F FFFF FFFF, and the most negative number is –256, represented by $80 0000 0000. 2-18 SC140 DSP Core Reference Manual...
Page 51: Two's Complement Word Representations
Signed Fractional Signed Integer Unsigned Integer $7FFF $7FFF $FFFF – 1.0 2 – – – $FFFE – $0001 $0001 – $0000 $0000 $FFFF $FFFF – 1 – – $0001 $8000 $8000 $0000 – – SC140 DSP Core Reference Manual 2-19...
Page 52: Multiplication
2.2.2.5.1 Unsigned Multiplication Unsigned multiplication (MPYUU, MACUU) and mixed unsigned-signed multiplication (MPYSU, MACSU) are used to support double precision, as described in Section 2.2.2.8, “Multi-Precision Arithmetic Support.” These instructions can be used for unsigned arithmetic multiplication. 2-20 SC140 DSP Core Reference Manual...
Page 53: Rounding Modes
LP was <1/2, or if LP = 1/2 and bit 16 was 0 (even). After rounding, the LP is cleared. If scaling down is selected, the HP is bits 39:17 and the LP is bits 16:0. If scaling up is selected, the HP is bits 39:15 and the LP is bits 14:0. SC140 DSP Core Reference Manual 2-21...
Page 54: Convergent Rounding (No Scaling)
X X . . X X X X X . . . X X X 0 1 1 0 0 0 0 ..0 0 0 32 31 16 15 32 31 16 15 *D0.l is always clear, performed during RND, MPYR, and MACR. Figure 2-5. Convergent Rounding (No Scaling) 2-22 SC140 DSP Core Reference Manual...
Page 55 LP is cleared. If scaling down is selected, the HP is bits 39:17 and the LP is bits 16:0. If scaling up is selected, the HP is bits 39:15 and LP is bits 14:0. SC140 DSP Core Reference Manual 2-23...
Page 56: Two's Complement Rounding (No Scaling)
X X . . X X X X X . . . X X X 0 1 1 0 0 0 0 ..0 0 0 32 31 16 15 32 31 16 15 *D0.l is always cleared, performed during RND, MPYR, and MACR. Figure 2-6. Two’s Complement Rounding (No Scaling) 2-24 SC140 DSP Core Reference Manual...
Page 57: Arithmetic Saturation Mode
DALU overflow bit set 1. In case of a 40-bit overflow which takes place in conjunction with arithmetic saturation, the constant being chosen is undefined, and it can be either the negative or positive constant. SC140 DSP Core Reference Manual 2-25...
Page 58: Multi-Precision Arithmetic Support
Fractional multiplication with signed × unsigned operands and 16-bit arithmetic right DMACSU shift of the accumulator before accumulation Figure 2-7 shows how the DMAC instruction is implemented. 16-bit Operand 16-bit Operand >> 16 Multiply Register Shifter 40-bit Accumulate Figure 2-7. DMAC Implementation 2-26 SC140 DSP Core Reference Manual...
Page 59: Fractional Double-Precision Multiplication
D0.h D1.l Unsigned × Signed macus D0,D1,D2 × D1.h D0.l (tfr D2,D4) Signed × Signed × D1.h D0.h dmacss D0,D1,D2 S Ext D2.e D2.h D2.l D4.l D3.l 64 bits Figure 2-8. Fractional Double-Precision Multiplication SC140 DSP Core Reference Manual 2-27...
Page 60: Fractional Mixed-Precision Multiplication
Integer multiplication with unsigned x unsigned operands IMPYHLUU Integer multiply unsigned x unsigned: first source from high portion, second from low portion IMACLHUU Integer multiply-accumulate unsigned x unsigned: first source from low portion, second from high portion 2-28 SC140 DSP Core Reference Manual...
Page 61: Signed Integer Double-Precision Multiplication
D0,D1,D2 D1.l D0.l Signed × Unsigned × impysu D0,D1,D3 D0.h D1.l Unsigned × Signed × imacus D0,D1,D3 D1.h D0.l D3.l aslw D2,D3 D3.h D3.l 32 bits AA0551 Figure 2-10. Signed Integer Double-Precision Multiplication SC140 DSP Core Reference Manual 2-29...
Page 62: Viterbi Decoding Support
Section 3.1.1, “Status Register (SR),” on page 3-1. Complementary AGU move operations are provided (VSL instructions). For a full description of the Appendix A, “Viterbi Shift Left Move (AGU) VSL,” Viterbi instructions, see on page A-422. 2-30 SC140 DSP Core Reference Manual...
Page 63: Address Generation Unit
Mj for any of the M0–M3 modifier registers All the Rn, Bn, SP, Ni, and Mj registers are referred to as AGU registers. All of the AGU registers are 32-bits. Figure 2-12 shows a block diagram of the AGU. SC140 DSP Core Reference Manual 2-31...
Page 64: Agu Block Diagram
All bit mask instructions are typically executed in two cycles and work on 16-bit data. This data can be a memory location or a portion (high or low) of a register. For more information, see Section 2.3.6, “Bit Mask Instructions.” 2-32 SC140 DSP Core Reference Manual...
Page 65 B register, choosing the correct result from the offset adder or the modulo adder. For more information, see Section 2.3.5, “Arithmetic Instructions on Address Registers.” SC140 DSP Core Reference Manual 2-33...
Page 66: Agu Programming Model
R8 / B0 R9 / B1 R10 / B2 R11 / B3 R12 / B4 R13 / B5 R14 / B6 R15 / B7 ADDRESS REGISTERS / BASE ADDRESS REGISTERS Figure 2-13. AGU Programming Model 2-34 SC140 DSP Core Reference Manual...
Page 67: Address Registers (R0-R15)
They are post-incremented on all the implicit PUSH operations and pre-decremented on all the implicit POP operations. Note: Both stack pointer registers must be initialized explicitly by the programmer after reset. SC140 DSP Core Reference Manual 2-35...
Page 68: Offset Registers (N0-N3)
When activating the modulo arithmetic, the contents of Mj specify the modulus. Each low address register can be used with each modifier register as programmed in the MCTL register. 2-36 SC140 DSP Core Reference Manual...
Page 69: Modifier Control Register (Mctl)
M2 used—Multiple wrap-around modulo addressing M3 used—Multiple wrap-around modulo addressing MCTL is initialized to zero at reset, setting a default linear mode for all Rn registers. All other AM field combinations are reserved and should not be used. SC140 DSP Core Reference Manual 2-37...
Page 70: Addressing Modes
The type of arithmetic used for updating R0-R7 is determined by programming the MCTL register. An example is: move.f (r3)+,d2. The data in the location identified by the value in r3 is moved to data register d2. Then the value in r3 is incremented by two. 2-38 SC140 DSP Core Reference Manual...
Page 71 32-bit offset and subtracted from the active stack pointer (NSP in Normal mode, ESP in Exception mode) to obtain the operand address. Thus, the displacement can range from [0] to [31/63] words or long words according to the access width. The contents of the SC140 DSP Core Reference Manual 2-39...
Page 72: Pc Relative Mode
20 bits and can range from [-1,048,576] to [1,048,574] words. In the DOSETUP instruction, the displacement occupies 16 bits of the instruction. The displacement for the start address (SA) can range from [-65,536] to [65,534] words. 2-40 SC140 DSP Core Reference Manual...
Page 73: Special Addressing Modes
An example is: , which transfers the 32-bit word stored at the other tfra osp,r2 (non-active) stack pointer to address register R2. SC140 DSP Core Reference Manual 2-41...
Page 74: Memory Access Width
In addition, an exception may be generated to identify that an unaligned access occurred. For more information, see Section 5.8, “Exception Processing,” on page 5-46. 2-42 SC140 DSP Core Reference Manual...
Page 75: Addressing Modes Summary
LC0, LC1 LC2, LC3 SA0, SA1 SA2, SA3 √ Address Register (Rn) — √ Address Modifier Register (Mj) — √ Base Address Register (Bn) — √ Address Offset Register (Ni) — √ Stack Pointer — SC140 DSP Core Reference Manual 2-43...
Page 76 Absolute Jump Address — xxxxxxxx (32 bits) √ √ √ Implicit Reference — Note: The “—” that appears in the “R0-R7 Uses MCTL” heading means that it is not applicable for that addressing mode. 2-44 SC140 DSP Core Reference Manual...
Page 77: Address Modifier Modes
M, thus defining a buffer with a lower and an upper address boundary. Each base address register (Bn register) is associated with an Rn register (B0 with R0, and so on). Each SC140 DSP Core Reference Manual 2-45...
Page 78: Modulo Addressing Example
$20, the modulus is $c, and r0 is $24. The operation is 36+14=50=38 in modulus 12, base address 32 (50–44 + 32 = 38). $0020 = B M = 12 $002c = B + M – 1 Figure 2-15. Modulo Addressing Example 2-46 SC140 DSP Core Reference Manual...
Page 79: Multiple Wrap-Around Modulo Addressing Mode
$000f, then M0 = 16. If r0 is initially $24 (36), the lower boundary is $20 (32) and the upper boundary is $2f (47). The memory access is done from address $26 (38), calculated by 36 + 66 = 102, 102–48=54, 54–3x16=6, 6+32=38. SC140 DSP Core Reference Manual 2-47...
Page 80: Arithmetic Instructions On Address Registers
AGU Compare for equal CMPGTA AGU Compare for greater than CMPHIA AGU Compare for higher (unsigned) DECA AGU Decrement register (affected by the modifier mode) DECEQA AGU Decrement and set T if result is zero 2-48 SC140 DSP Core Reference Manual...
Page 81: Bit Mask Instructions
Only a single bit mask instruction is allowed in one execution set since only one execution unit exists for these instructions. A subgroup of the bit mask instructions (BMTSET) supports hardware semaphores. For more information, see Section 2.3.6.1, “Bit Mask Test and Set (Semaphore Support) Instruction.” SC140 DSP Core Reference Manual 2-49...
Page 82: Bit Mask Test And Set (Semaphore Support) Instruction
BMTSET operation. As a result of the non-exclusive write indication, the T bit is set, signalling that the resource may not be available, thereby avoiding a hazard condition. 2-50 SC140 DSP Core Reference Manual...
Page 83: Semaphore Hardware Implementation
Table 2-25 lists the move instructions. The suffix just before the period in the MOVE nomenclature indicates the following: • None = Signed • U = Unsigned • S = Scaling and limiting (saturation) enabled SC140 DSP Core Reference Manual 2-51...
Page 84: Agu Move Instructions
Viterbi shift left—specialized move to support Viterbi kernel VSL.2W Viterbi shift left—specialized move to support Viterbi kernel VSL.4F Viterbi shift left—specialized move to support Viterbi kernel VSL.4W Viterbi shift left—specialized move to support Viterbi kernel 2-52 SC140 DSP Core Reference Manual...
Page 85: Integer Move Instructions
MOVE.2L may also be considered fractional moves since alignment in the destination register is the same for integer long moves and fractional long moves. A schematic representation of fractional moves from memory to 40-bit data registers is shown in Figure 2-17. SC140 DSP Core Reference Manual 2-53...
Page 86: Fractional Move Instructions
In one case of the MOVE.L instruction, two extensions belonging to two consecutive data registers are moved concurrently from the registers to the memory as part of a 32-bit access. 2-54 SC140 DSP Core Reference Manual...
Page 87: Memory Interface
(8 bits), word (16 bits), long word (32 bits), or double-long word and four-word (64 bits). One of four control signals will indicate to the memory which access width is needed for each access. • Multi-byte memory accesses must support both endian modes. SC140 DSP Core Reference Manual 2-55...
Page 88: Sc140 Endian Support
Figure 2-19. Endian Example 2.4.1.1 SC140 Bus Structure The entire memory space of the SC140 core is unified. The memory supports two parallel 64-bit data accesses and one 128-bit program fetch. All can occur in parallel. 2-56 SC140 DSP Core Reference Manual...
Page 89: Memory Organization
07 08 05 06 03 04 01 02 11 22 33 44 cc dd ee ff cc dd ee ff 11 22 33 44 16 ($10) 16 ($10) Figure 2-21. Memory Organization of Big and Little Endian Mode SC140 DSP Core Reference Manual 2-57...
Page 90: Data Moves
Long type access, writing or reading 32-bit operands. • Word type access, writing or reading 16-bit operands. • Byte type access, writing or reading 8-bit operands. Figure 2-22 shows an example of data transfer in big and little endian modes. 2-58 SC140 DSP Core Reference Manual...
Page 91: Data Transfer In Big And Little Endian Modes
For single-register moves, assuming an equivalent memory map in big and little endian modes, the byte organization on the buses is identical in both modes. However, the memory subsystem must route the data bus bytes to different memory addresses for each supported endian mode. SC140 DSP Core Reference Manual 2-59...
Page 92: Multi-Register Moves
Note that the data word from d0, $0102, is at a different address for the two modes. If the data bus were modified by the core to $03040102, then the memory for little endian mode would look like: Address Data 2-60 SC140 DSP Core Reference Manual...
Page 93: Multi-Register Transfer In Big And Little Endian Modes
For more information about the VSL instructions, refer to Table 2-27 on page 2-64, Appendix A, “Viterbi Shift Left Move (AGU) VSL,” on page A-422.. SC140 DSP Core Reference Manual 2-61...
Page 94: Instruction Word Transfers
$01 data $b0byte address $01 data $a0 byte address $02 data $c0byte address $02 data $d0 byte address $03 data $d0byte address $03 data $c0 byte address $04 data $e0byte address $04 data $f0 ..2-62 SC140 DSP Core Reference Manual...
Page 95: Instruction Moves In Big And Little Endian Modes
Figure 2-25. Instruction Moves in Big and Little Endian Modes The Program Bus contents always appear as eight 16-bit little endian packed instructions, the memory system performing a word (instruction) reversal in the case of big endian (program bus only). SC140 DSP Core Reference Manual 2-63...
Page 96: Memory Access Behavior In Big/Little Endian Modes
D3 = MOVE.L A0 = A A0 = D Example: MOVE.L D0, (R0) MOVEU.L A1 = B A1 = C MOVES.L A2 = C A2 = B A3 = D A3 = A D0 = 2-64 SC140 DSP Core Reference Manual...
Page 97 A3 = D A3 = C A4 = E A4 = F D1 = A5 = F A5 = E A6 = G A6 = H D2 = A7 = H A7 = G D3 = SC140 DSP Core Reference Manual 2-65...
Page 98 2. Data selected according to VF2 bit in SR, selects D3.l<<1 if VF2=1, D1.L<<1 if VF2=0 3. Data selected according to VF1 bit in SR, selects D3.H<<1 if VF1=1, D1.H<<1 if VF1=0 4. Data selected according to VF3 bit in SR, selects D3.H<<1 if VF3=1, D1.H<<1 if VF3=0 2-66 SC140 DSP Core Reference Manual...
Page 99: Stack Support Instructions In Big And Little Endian Modes
Register Operands Big Endian Endian BMCHG.W A0 = A A0 = B Example: BMSET.W #$1234, (A0) BMCLR.W A1 = B A1 = A BMSET.W BMTSTS.W Data = BMTSTC.W Mask = BMTSET.W NOT.W AND.W OR.W EOR.W SC140 DSP Core Reference Manual 2-67...
Page 100: Control Instructions In Big And Little Endian Modes
Interrupt Service A3 = D A3 = A A4 = E A4 = H SR = A5 = F A5 = G A6 = G A6 = F A7 = H A7 = E 2-68 SC140 DSP Core Reference Manual...
Page 101: Control Registers
When a subroutine or exception is serviced, the status register is pushed onto the stack. The following instructions implicitly push the SR onto the stack: • JSR/D • BSR/D Any exception or interrupt implicitly pushes the SR onto the stack, including exceptions that are triggered by the following instructions: • TRAP SC140 DSP Core Reference Manual...
Page 102: Status Register Description
#4 is enabled. At the start 1 = Hardware loop #4 enabled of an ISR, the SR (including the LF3 bit) is pushed onto the software stack and the LF3 bit is cleared. This bit is cleared at core reset. SC140 DSP Core Reference Manual...
Page 103 The interrupt mask bits are set at core IPL 6–7 IPL 0–5 reset. IPL 7 IPL 0–6 For a detailed description of interrupt service, refer to Section 5.8, “Exception IPL 0–7 Processing,” on page 5-46. An IPL0 exception is always masked. SC140 DSP Core Reference Manual...
Page 104 MAX2VIT result. For more information, see MAX2VIT and VSL in Appendix A, “SC140 DSP Core Instruction Set.” These bits are cleared at core reset. Reserved Bit 7 SC140 DSP Core Reference Manual...
Page 105 0 = Convergent rounding selected Bit 3 of rounding performed by the DALU 1 = Two’s complement rounding selected during arithmetic operations that involve rounding. SeeSection 2.2.2.6, “Rounding Modes.” This bit is cleared at core reset. SC140 DSP Core Reference Manual...
Page 106 Conditional instructions (such as JT, JF, BT, BF, IFT, and others) test the T-bit, and execute accordingly. This bit is cleared during core reset as well as at the start of an exception service routine. SC140 DSP Core Reference Manual...
Page 107: Exception And Mode Register (Emr)
Illegal instruction opcode Figure 3-2 displays the bit configuration of the execution and mode register BIT 31 TYPE RESET BIT 15 BIT 0 NMID DOVF ILST ILIN TYPE RESET Figure 3-2. Exception and Mode Register (EMR) SC140 DSP Core Reference Manual...
Page 108: Emr Description
If the OVE bit is set, the clearing operation should only be performed during the overflow exception service routine. Due to pipeline effects, the overflow exception is not serviced immediately after the instruction that caused the overflow condition. SC140 DSP Core Reference Manual...
Page 109 The bit is cleared by writing back 1 to it, as explained in Section 3.1.2.1, “Clearing EMR Bits.” This clearing operation should only be performed during the illegal exception service routine. ILIN is cleared at reset. SC140 DSP Core Reference Manual...
Page 110: Clearing Emr Bits
PLL as well as clocks, named PCTL0 and PCTL1. The definition and usage of these registers is chip specific. In systems where the PLL is controlled without these registers, they cannot be used as general purpose registers. 3-10 SC140 DSP Core Reference Manual...
Page 111: Emulation And Debug (Eonce)
The EOnCE module provides system-level debugging for real-time systems with the ability to: • Maintain a running log and trace when tasks and interrupts are executed. • Debug the operation of real-time operating systems (RTOS). SC140 DSP Core Reference Manual...
Page 112: Overview Of The Combined Jtag And Eonce Interface
A typical SC140SoC uses the JTAG TAP controller for standard defined testing compatibilities and for single/multi-core EOnCE control and EOnCE interconnection control. In a multi-core device the EOnCE modules interconnect in a chain and are configured and controlled by the JTAG port (see Figure 4-1). SC140 DSP Core Reference Manual...
Page 113: Jtag Scan Paths
Selects the ID Register. Allows the manufacturer, part number and version of a component to be identified. CLAMP Selects the Bypass Register. Allows signals driven from the component pins to be determined from the Boundary Scan Register. SC140 DSP Core Reference Manual...
Page 114 Figure 4-2 shows the TAP controller state machine, and Table 4-3 shows the states associated with each scan path. The Test Mode Select ) pin determines whether an instruction register scan or a data (TMS register scan is performed. SC140 DSP Core Reference Manual...
Page 115: Tap Controller State Machine
TAP to exit the Test-Logic-Reset and move through the appropriate states. From the Run-Test/Idle state, an instruction register scan or a data register scan can be issued to transition through the appropriate states. SC140 DSP Core Reference Manual...
Page 116: Activating The Eonce Through The Jtag Port
To activate the n-th core in the cascade, which is the closest to and the farthest from , the data is 1,0,0,0,...,0 (first a one, then n-1 zeros). If the data is 1,0,1,0,0..0 then both the n-th and the n-2th cells are selected. SC140 DSP Core Reference Manual...
Page 117: Debug_Request And Enable_Eonce Commands
JTAG into shift-dr and shift the required data, which is to be written into the EDCA0_CTRL, via . If the command is “read some register,” then the DR chain must be passed again and the contents of the register are shifted out through the output. SC140 DSP Core Reference Manual...
Page 118: Reading And Writing Eonce Registers Via Jtag
In case other devices participate in the transaction, the full shift register length should be used, using the convention outlined in Figure 4-5. From the IEEE 1149.1 standard point of view, some of the EOnCE registers have different “read” and “write” views. SC140 DSP Core Reference Manual...
Page 119: Accessing Eonce Registers Through Jtag
(relevant bits) (don’t care bits) internal shift register (B) EOnCE register read (capture) operation through JTAG EOnCE register 24 zeros (bits captured as zero) (relevant bits) internal shift register Figure 4-5. Accessing EOnCE registers through JTAG SC140 DSP Core Reference Manual...
Page 120: Main Capabilities Of The Eonce Module
DSP device. Some of these signals have multiple functions programmed by the EE Signals Control Register (EE_CTRL). See Section 4.7.6, “EE Signals,” for further information. 4-10 SC140 DSP Core Reference Manual...
Page 121: Eonce Dedicated Instructions
When the EE0 signal causes the core to enter debug state, the signal must be asserted until the user receives debug acknowledgement. Asserting the EE0 pin or the JTAG DEBUG_REQUEST instruction signal during reset until getting debug acknowledge will place the core into debug processing state before the first VLES fetch. SC140 DSP Core Reference Manual 4-11...
Page 122: Debug Exception
To do this, the CHOOSE_EONCE and DEBUG_REQUEST instructions must have already been executed through the JTAG port, thereby enabling the EOnCE, entering the core into debug state. Figure 4-7 shows a possible flow for software downloading. 4-12 SC140 DSP Core Reference Manual...
Page 123: Software Downloading
The CORE_CMD register is selected. Write into the CORE_CMD register with a MOVE instruction from the core register to a memory location. The memory location is written with the program data. Figure 4-7. Software Downloading SC140 DSP Core Reference Manual 4-13...
Page 124: Eonce Events
Trace Transaction The emulator writes a record to the trace buffer An EC signal (EC0 or EC1) is asserted MARK The core executes a MARK instruction A change of flow occurs during program execution 4-14 SC140 DSP Core Reference Manual...
Page 125: Eonce Actions
• EDCA • Enable other EDCAs • Enable the EDCD • Enable the counter External EDCA • Enable other EDCAs • Enable the EDCD • Enable the counter Trace Buffer Full ERCV ETRSMT VLES SC140 DSP Core Reference Manual 4-15...
Page 126: Eonce Enabling And Power Considerations
The various EOnCE units include a number of registers. The units, the tasks they perform, and the corresponding registers are described in the sections that follow. 4.5.1 EOnCE Controller The EOnCE controller performs the following functions: • Reading and writing EOnCE registers through JTAG 4-16 SC140 DSP Core Reference Manual...
Page 127: Eonce Controller Block Diagram
EOnCE monitor and control register ERCV EOnCE receive register ETRSMT EOnCE transmit register EE_CTRL EE signals control register CORE_CMD EOnCE core command register PC_EXCP PC of the execution set causing illegal or overflow exception SC140 DSP Core Reference Manual 4-17...
Page 128: Event Counter
When the core is in debug state, the event counter does not count core clocks. The event counter programming model includes three registers: • Event counter register (ECNT_CTRL) • Downcount event counter value register (ECNT_VAL) • Extension counter value register (ECNT_EXT) 4-18 SC140 DSP Core Reference Manual...
Page 129: Event Counter Block Diagram
Register Name Description ECNT_CTRL Event counter control register ECNT_VAL Event counter value register (32-bit) ECNT_EXT Extension counter value register (32-bit) The functionality of the event counter registers is described in Section 4.8, “Event Counter Registers.” SC140 DSP Core Reference Manual 4-19...
Page 130: Event Detection Unit (Edu)
Section 4.5.4, “Event Selector (ES).” • Enable another EDCA or EDCD • Enable the counter • Generate a counter event • Toggle an EE pin (one EE pin assigned to each EDCA or EDCD) 4-20 SC140 DSP Core Reference Manual...
Page 131: Event Detection Unit Block Diagram
EDCD EventD Event0 Event1 Event2 Event5 Count event from EDCA6,7 (ext.) Event6,7 (external) Count event (from Counter) Debug State Event Debug Exceptio Selector Enable Trace Disable Trace Figure 4-10. Event Detection Unit Block Diagram SC140 DSP Core Reference Manual 4-21...
Page 132: Address Event Detection Channel (Edca)
Two 32-bit comparators are used to compare the core address buses and the reference values programmed into the reference value registers EDCAi _REFA and EDCAi _REFB. Each comparator is capable of detecting one of the following four conditions: • Equal • Not equal • Less than 4-22 SC140 DSP Core Reference Manual...
Page 133 EDCA control register EDCAi_REFA EDCA reference value register A EDCAi_REFB EDCA reference value register B EDCAi_MASK EDCA mask register The functionality of the EDCA registers is described in Section 4.9.1, “Address Event Detection Channel (EDCA).” SC140 DSP Core Reference Manual 4-23...
Page 134: Data Event Detection Channel (Edcd)
Table 4-9. EDCD Register Set Register Name Description EDCD_CTRL EDCD control register EDCD_MASK EDCD mask register EDCD_REF EDCD reference value register The functionality of the EDCD registers is described in Section 4.9.2, “Data Event Detection Channel (EDCD).” 4-24 SC140 DSP Core Reference Manual...
Page 135: Optional External Event Detection Address Channels
• Entry into Debug state • Execution of a Debug exception • Enable or disable program tracing 1. They can be programmed individually or combined with other simultaneous events SC140 DSP Core Reference Manual 4-25...
Page 136: Trace Unit
The trace unit is used to store information about a running application without halting its execution. The user can select the addresses to be stored in the trace unit from a wide selection that includes: • Change-of-flow instructions — All Change-of-flow instructions — Call/return from subroutine instructions 4-26 SC140 DSP Core Reference Manual...
Page 137 The PC of every execution set issued. • The last address for short hardware loops and the last address followed by the start address for long hardware loops. • The PC of each execution set that includes the MARK instruction. SC140 DSP Core Reference Manual 4-27...
Page 138: Change Of Flow And Interrupt Tracing
The following change of flow instructions are those that can be traced: — BT, BF, BTD, BFD — BRA, BRAD — JMP JMPD — JT, JF, JTD, JFD — JSR, JSRD — BSR, BSRD — RTS, RTSD — RTSTK, RTSTKD — RTE, RTED 4-28 SC140 DSP Core Reference Manual...
Page 139: Writing To The Trace Buffer
Section 4.7.3, “EOnCE Monitor and Control Register (EMCR),” Section 4.6.1, “Reading or Writing EOnCE Registers Using Core Software,” for further details. 4.5.5.4 Trace Unit Programming Model The trace unit contains the following registers, as shown in Table 4-11. SC140 DSP Core Reference Manual 4-29...
Page 140: Eonce Register Addressing
Section 4.2.6, “Reading/Writing EOnCE Registers Through JTAG,” each EOnCE unit has a shift register supporting the EOnCE registers of this unit. In some cases, the “shift width” of the EOnCE register is longer than its actual width. 4-30 SC140 DSP Core Reference Manual...
Page 141: Eonce Register Addressing Offsets
EDCA3 control register EDCA4_CTRL EDCA4 control register EDCA5_CTRL EDCA5 control register Reserved address Reserved address EDCA0_REFA EDCA0 reference value A EDCA1_REFA EDCA1 reference value A EDCA2_REFA EDCA2 reference value A EDCA3_REFA EDCA3 reference value A SC140 DSP Core Reference Manual 4-31...
Page 142 EDCD_REF EDCD reference value EDCD_MASK EDCD mask register ....Reserved addresses ..ECNT_CTRL Counter control register ECNT_VAL Counter value register ECNT_EXT Extension counter value ....Reserved addresses ..ESEL_CTRL Selector control register 4-32 SC140 DSP Core Reference Manual...
Page 143: Reading Or Writing Eonce Registers Using Core Software
If the bit is set, this indicates that the last EOnCE command was successfully executed. This bit is reset each time a new command is shifted from the JTAG port to the EOnCE. SC140 DSP Core Reference Manual 4-33...
Page 144: Real-Time Data Transfer
If the software writes and then reads a given EOnCE register, a NOP or other instruction must be inserted before the read instruction in order to read back the value just written. 4-34 SC140 DSP Core Reference Manual...
Page 145 The ERCV registers are only writable using the JTAG port. • PC_LAST and PC_NEXT can only be read by the JTAG port. • The CORE_CMD register can only be written by the JTAG port in debug state. SC140 DSP Core Reference Manual 4-35...
Page 146: Eonce Controller Registers
Read/Write Command — Specifies the 0 = Write the data associated with the command into Bit 9 direction of data transfer. the register specified by REGSEL. 1 = Read the data contained in the register specified by REGSEL. 4-36 SC140 DSP Core Reference Manual...
Page 147: Eonce Status Register (Esr)
After entering debug state, the appropriate bit is set when a new event occurs that could cause the core to enter debug state. Figure 4-16 displays the bit configuration of the ESR. BIT 31 CORES PCKILL RCV TRSMT TBFULL NOCHOF REVNO CORETP DRTBFULL TYPE RESET SC140 DSP Core Reference Manual 4-37...
Page 148: Eonce Status Register (Esr)
The TRSMT bit is set when the MSB has been written without checking if the LSB part has been written. The bit is cleared by EOnCE when the host has finished reading the content of the ETRSMT register. 4-38 SC140 DSP Core Reference Manual...
Page 149 Bit 14 debug exception as a result of EE4 assertion. It is cleared by the EOnCE when the core exits debug state, or when the DIS bit in EMCR is reset by the user. SC140 DSP Core Reference Manual 4-39...
Page 150 Bit 0 debug exception as a result of detection by EDCA0. It is cleared by the EOnCE when the core exits debug state, or when the DIS bit in EMCR is reset by the user. 4-40 SC140 DSP Core Reference Manual...
Page 151: Eonce Monitor And Control Register (Emcr)
If this bit is set and the RCV bit is set by the EOnCE, a debug exception is issued. The core interrupt service routine (ISR) determines the reason for the interrupt and reads the content of the ERCV register. SC140 DSP Core Reference Manual 4-41...
Page 152 EDCA1. It should be cleared by the user. EDCAST0 EDCA0 Status — Sticky bit that is set by the EOnCE upon event detection by Bit 0 EDCA0. It should be cleared by the user. 4-42 SC140 DSP Core Reference Manual...
Page 153: Eonce Receive Register (Ercv)
5. The TRSMT bit is cleared on completion of the read by the host debugger. If the TRSINT bit in the EMCR is set, the core is interrupted by a debug exception, informing the core that further data can be transmitted. SC140 DSP Core Reference Manual 4-43...
Page 154: Ee Signals
ERCV register through the JTAG. It is negated when the core finishes reading the Most Significant Part of the ERCV register. 4-44 SC140 DSP Core Reference Manual...
Page 155: Ee Signals As Inputs
Figure 4-18 displays the bit configuration of the EE signals control register. Shaded bits are reserved and should be initialized with zeros for future software compatibility. BIT 15 BIT 0 EEDDEF EE5DEF EE4DEF EE3DEF EE2DEF EE1DEF EE0DEF TYPE RESET Figure 4-18. EE Signals Control Register (EE_CTRL) SC140 DSP Core Reference Manual 4-45...
Page 156 Programmed as an input to the EOnCE according to the programming of the EDU and the ES, EE3 can be programmed to enable EDCA3 or to generate one of the EOnCE events. EE3 cannot disable EDCA3. 4-46 SC140 DSP Core Reference Manual...
Page 157 Section 5.7, “Processing States,” on page 5-41. When programmed as a debug request, EE0 can also enable EDCA0 or generate an EOnCE event if EDCA0 or the ES are programmed in this manner. SC140 DSP Core Reference Manual 4-47...
Page 158: Core Command Register (Core_Cmd)
In general, core commands should not perform illegal operations. In case a core command generated an exception (such as an illegal exception), the exception will be serviced only after the core exits debug state. 4-48 SC140 DSP Core Reference Manual...
Page 159: Pc Of The Exception Execution Set (Pc_Excp)
PC_DETECT captures the correct PC of the VLES that triggered the entry into debug state if all the following conditions are met: • An event was detected on XABA/B and/or XDBA/B by an enabled EDCA/D channel. SC140 DSP Core Reference Manual 4-49...
Page 160: Event Counter Registers
1111 to the ECNTEN bits of the control register. It can also be enabled by specifying an event. The profiler can exploit this capability for cycle count operations to 4-50 SC140 DSP Core Reference Manual...
Page 161 Bit 9 1 = Reserved for test Extended Mode of Operation Bit — 0 = ECNT operates in regular mode Bit 8 Section 4.5.2, “Event Counter,” 1 = ECNT operates in extended mode page 4-18. SC140 DSP Core Reference Manual 4-51...
Page 162: Event Counter Value Register (Ecnt_Val)
ECNT_VAL is a down-counter. The MSB is always zero, so the range is from $7FFF FFFF to $0000 0000. When the register is written, the MSB should be written to zero for software compatibility. 4-52 SC140 DSP Core Reference Manual...
Page 163: Extension Counter Value Register (Ecnt_Ext)
These inputs are assumed to be synchronized to the core clock and support a counting rate up to the core frequency. EC0 and EC1 use is derivative-dependent. SC140 DSP Core Reference Manual 4-53...
Page 164: Event Detection Unit (Edu) Channels And Registers
Figure 4-21 displays the configuration of the EDCAi_CTRL register. BIT 15 BIT 0 EDCAEN CBCS CACS TYPE RESET Figure 4-21. EDCA Control Register (EDCA _CTRL) Table 4-19 describes the EDCAi_CTRL fields. Table 4-19. EDCA_CTRL Description Name Description Settings Reserved Bits 14-15 4-54 SC140 DSP Core Reference Manual...
Page 165 • Only comparator A condition is detected. • Only comparator B condition is detected. • Both comparator A and comparator B conditions are detected. • Either comparator A or comparator B conditions are detected. SC140 DSP Core Reference Manual 4-55...
Page 166 EDCAs are required. When configuring two EDCAs to detect a watchpoint to an address range, one EDCA should be configured to detect the range on bus A, and the other EDCA to detect 4-56 SC140 DSP Core Reference Manual...
Page 167: Edca Mask Register (Edcai_Mask)
The masked address value is then compared to the EDCAi_REFA and EDCAi_REFB registers. For example, the EDCAi_MASK register can be used to detect accesses to a memory region with several address aliases. SC140 DSP Core Reference Manual 4-57...
Page 168: Data Event Detection Channel (Edcd)
The shaded bits are reserved and should be initialized with zeros for future software compatibility. Figure 4-22. EDCD Control Register (EDCD_CTRL) Table 4-20 describes the EDCD_CTRL fields. Table 4-20. EDCD_CTRL Description Name Description Settings Reserved Bits 14-15 Reserved Bits 13–10 4-58 SC140 DSP Core Reference Manual...
Page 169 32 bits of the masked data. One or two comparisons are performed with logical OR among them, depending on the access resolution (long or double-long). Reserved Bit 7 SC140 DSP Core Reference Manual 4-59...
Page 170 Access Type Selection — The ATS bit 0 = Read Bit 0 determines whether the memory access 1 = Write is read or write. 4-60 SC140 DSP Core Reference Manual...
Page 171: Edcd Reference Value Register (Edcd_Ref)
The 8-bit control register ESEL_CTRL controls the operation of the ES, which is programmed in the following order: 1. Reset the event selector mask registers. 2. Program the ESEL_CTRL register. 3. Program the appropriate event selector mask registers. SC140 DSP Core Reference Manual 4-61...
Page 172 Each of the following event selector registers can enable the system to configure what debug events (EDCA event, EE event etc.) will cause the outcome controlled by that register (entry into debug state, debug exception etc.). 4-62 SC140 DSP Core Reference Manual...
Page 173: Event Selector Mask Debug State Register (Esel_Dm)
SELDM bit in the ESEL_CTRL. For more information, see Section 4.10.1, “Event Selector Control Register (ESEL_CTRL),” on page 4-61. If all the bits are set to zero, the ES does not enter debug state. SC140 DSP Core Reference Manual 4-63...
Page 174: Event Selector Mask Debug Exception
If multiple sources are configured to enable trace, they are ANDed or ORed according to the value of the SELETB bit in the ESEL_CTRL. If all the bits are set to zero, the ES does not enable trace. The same event cannot be configured to both enable and disable tracing. 4-64 SC140 DSP Core Reference Manual...
Page 175: Event Selector Mask Disable Trace Register (Esel_Dtb)
TINT - trace the interrupt point and destination PC of interrupts and exceptions (including the TRAP, and ILLEGAL instructions) TEXEC and TMARK can only be activated on their own, without other tracing options enabled. SC140 DSP Core Reference Manual 4-65...
Page 176 1, while the LSB of all other words in a package is 0. This allows decoding the trace buffer contents when the trace buffer is set to trace different cases, when all programmed information could not be written to the trace buffer at the same time. 4-66 SC140 DSP Core Reference Manual...
Page 177 When both counter mode bits (TCOUNT and TCNTEXT) are set, the event counter register is first written followed by the extension counter register SC140 DSP Core Reference Manual 4-67...
Page 178 (the address of the first instruction in the execution set) and the target address of the change-of-flow instruction. 4-68 SC140 DSP Core Reference Manual...
Page 179: Trace Buffer Read Pointer Register (Tb_Rd)
This 32-bit register is used to read the contents of the trace buffer. For details, see Section 4.5.5.3, “Reading the Trace Buffer (TB_BUFF).” It is a pipeline register inside the core, not the off-core trace buffer. SC140 DSP Core Reference Manual 4-69...
Page 180 Trace Unit Registers 4-70 SC140 DSP Core Reference Manual...
Page 181: Pipeline
Fetch stage • Dispatch stage • Address generation stage • Execution stage The first three stages are implemented in the program sequencer unit (PSEQ). The last two stages are implemented in the AGU and DALU, respectively. SC140 DSP Core Reference Manual...
Page 182: Instruction Pipeline Stages
SC140 core instruction timing, see Section 5.3, “Instruction Timing,” on page 5-14. 5.1.1 Instruction Pipeline Stages Figure 5-1 illustrates the five instruction pipeline stages. Pre-fetch Fetch Dispatch Address Generation Execution Figure 5-1. Instruction Pipeline Stages SC140 DSP Core Reference Manual...
Page 183: Pipeline Example
Read source operands to DALU • Read source register for memory store operations • Perform data calculations (multiply and add) • Write DALU results to destination registers • Write destination register for memory load operations SC140 DSP Core Reference Manual...
Page 184: Instruction Pre-Fetch And Fetch
DALU instructions. However, in the AGU, the address generation stage includes updating the address pointers as well as the actual memory accesses (driving the address and the read/write strobes). The AGU is also responsible for address calculation when a change-of-flow operation takes place. SC140 DSP Core Reference Manual...
Page 185: Execution
A second case is illustrated in Example 5-2, which shows a six-instruction execution set that executes in one clock cycle. Example 5-2. Grouping Six SC140 Instructions in an Execution Set MOVE.W(R0)+N3,D2 MOVE.L D0,R1 MAC D0,D1,D7 MAC D3,D4,D6 MACR D0,D2,D5 ADR D3,D4 DALU DALU DALU DALU Instr Instr Instr Instr Instr Instr SC140 DSP Core Reference Manual...
Page 186: Grouping Types
Figure 5-2 illustrates the serial and prefix methods for the SC140 grouping mechanism: Inst. #1 Inst. #2 Inst. #3 Serial grouping Prefix word(s) Inst. #1 Inst. #2 Inst. #3 Prefix grouping Figure 5-2. Instruction Grouping Methods SC140 DSP Core Reference Manual...
Page 187: Serial Grouping
The grouping information encoded in the prefix includes the number of words to be grouped (including the number of prefix words) minus one. Valid values are from 0 to 7. A value of 0 corresponds to a NOP instruction that is not dispatched. SC140 DSP Core Reference Manual...
Page 188: Prefix Types
For a description of what conditional execution options are available, see Section 5.2.3, “Conditional Execution.” For a description about the function of HW loop support with LPMARK, see Section 5.4, “Hardware Loops.” SC140 DSP Core Reference Manual...
Page 189: One-Word Low Register Prefix
Table 5-4 displays the conditional IFc syntax. In the table, [inst] represents optional additional instructions. Refer to Section 7.5.3, “Prefix Grouping Rules,” on page 7-11 for the IFc programming rules. Table 5-4. Conditional IFc Syntax Assembly Syntax Meaning [IFA] inst [inst] Unconditional execution of the VLES SC140 DSP Core Reference Manual...
Page 190: Prefix Selection Algorithm
A two-word prefix is generated only when high register banks are used in the execution set. The assembler encodes the execution set according to these principles, as shown in Figure 5-3. 5-10 SC140 DSP Core Reference Manual...
Page 191: Low Register Prefix Selection Algorithm
Type 1 instructions, except for instruction be the last in a single Type 2 or Type 3 VLES? instruction? Continue Use a one-word No prefix is low-register prefix. needed. Figure 5-3. Low Register Prefix Selection Algorithm SC140 DSP Core Reference Manual 5-11...
Page 192: Instruction Reordering Within An Execution Set
The position of a multi-word instruction is defined as the position of its first word. Example 5-3 shows the positions occupied by 3 one-word (1w) instructions and 2 two-word (2w) instructions grouped with a one-word prefix: 5-12 SC140 DSP Core Reference Manual...
Page 193 If no one-word instructions are included in the set, the assembler inserts a NOP instruction. Example 5-5 illustrates such a case. Example 5-5. Set of 2 Two-word Instructions Requiring a NOP MOVE #xxxx,D0 MOVE #xxxx,D1 SC140 DSP Core Reference Manual 5-13...
Page 194: Instruction Timing
This timing is for the current SC140 implementation, and may change with future implementations. Interrupt timing and memory access timing is also discussed in this section. 5-14 SC140 DSP Core Reference Manual...
Page 195: Sequential Instruction Timing
All bit mask (BMU) instructions execute in two cycles on registers and memory (zero-wait-states without contention) with simple addressing modes. However, if a pre-calculation is required, such as an SP offset, a third cycle is added. SC140 DSP Core Reference Manual 5-15...
Page 196: Dalu Instruction Timing
This type of instruction takes two clock cycles to execute for the simple addressing modes, and three clock cycles for the addressing modes that require pre-calculation of the address. Refer to Appendix A, “SC140 DSP Core Instruction Set,” for a full description of the bit mask instructions. 5-16 SC140 DSP Core Reference Manual...
Page 197: Change-Of-Flow Instruction Timing
Branch if false Branch if false (delayed) Branch BRAD Branch (delayed) Branch to subroutine BSRD Branch to subroutine (delayed) Branch if true Branch if true (delayed) Jump if false Jump if false (delayed) Jump SC140 DSP Core Reference Manual 5-17...
Page 198: Direct, Pc-Relative, And Conditional Cof
(meaning the change-of-flow operation is taken), always take an additional three cycles. When a conditional change-of-flow is determined as not taken (meaning the condition is false), there are no additional cycles. 5-18 SC140 DSP Core Reference Manual...
Page 199: Delayed Cof
An execution set is not necessarily aligned to a fetch set, and can overlap two fetch sets. The core keeps two fetch sets in a buffer, so this is not normally a problem. However, when a SC140 DSP Core Reference Manual 5-19...
Page 200: Number Of Cycles Needed By Change-Of-Flow Instructions
BRA, BSR BRAD 4 – C BSRD 4 – C < 4 ≥ 4 1+ C Jc/Bc Jump is taken. Jump is not taken. JcD/BcD 4 – C Jump is taken. Jump is not taken. 5-20 SC140 DSP Core Reference Manual...
Page 201: Memory Access Timing
The intent of the following section is to describe the timing for memory accesses generated by instructions in the same execution set. In some examples, no problems arise since the memory accesses fall into different cycles. In other examples, memory contention can occur. SC140 DSP Core Reference Manual 5-21...
Page 202: Memory Access Examples
Two memory writes to the same location are not allowed per Section 7.6, “Dynamic Programming Rules.” The following description is assumes a simple memory without write buffers, where the memory system executes all accesses on a 5-22 SC140 DSP Core Reference Manual...
Page 203 Cycle 2. The BMU write operation that accesses the same location in memory takes place at Cycle 3. Example 5-10. Execution Set Containing One Bit Mask Instruction BMSET.W #$0080,(SP-2) MOVE.W D2,($8200) ;Cycle 1: write to ($8200) ;Cycle 2: read from (SP-2) ;Cycle 3: write to (SP-2) SC140 DSP Core Reference Manual 5-23...
Page 204: Implicit Push/Pop Memory Timing
(or for one program access and one data access). Stalls can also occur if the memory itself is not zero-wait-states, which may be a characteristic of the memory technology (such as flash or DRAM), or may occur with off-chip memory. 5-24 SC140 DSP Core Reference Manual...
Page 205: Hardware Loops
The DOSETUPn label instruction initializes the SAn register with the start address. The LOOPSTARTn assembly directive also marks the start address and must be placed at the same address as the label of the DOSETUPn instruction. SC140 DSP Core Reference Manual 5-25...
Page 206: Loop Counter Registers (Lcn)
LPMARKA and LPMARKB — Two marker bits in the prefix words that identify different looping conditions. The LPMARK bits are set automatically by the assembler based on the LOOPSTARTn and LOOPENDn assembly directives, and are not written by the programmer. 5-26 SC140 DSP Core Reference Manual...
Page 207: Loop Initiation And Execution
In short loops, one or two execution sets are stored in internal buffers and repeated the appropriate number of times according to the value stored in LCn. No program fetches are required for short loops. SC140 DSP Core Reference Manual 5-27...
Page 208: Loop Nesting
The BREAK instruction also causes the active loop to terminate. The program address bus is loaded with the address specified by the BREAK instruction. The loop terminates (LFx is cleared) regardless of the value of LCn, which is not changed. 5-28 SC140 DSP Core Reference Manual...
Page 209: Loop Control Instructions
The last address information is encoded in the LPMARK prefix bits for long loops. The assembler normally places the LPMARKB bit at LA-2. For special cases, such as a SKIPLS SC140 DSP Core Reference Manual 5-29...
Page 210 = sub d5,d4,d4 inc d7 The following is an example of a short loop in two execution sets. Example 5-14. Short Loop, Two Execution Sets doensh0#$10 loopstart0 d0,d1,d2 move.w (r0)+,d0 LPMARKB d5,d6,d4 move.w (r1)+,d5 Loop body loopend0 5-30 SC140 DSP Core Reference Manual...
Page 211 The assembler sets the appropriate LPMARK bits, adding a prefix word with the loopstart or loopend information, if necessary. In disassembly, these LPMARK bits (if used) appear preceding the normal disassembled mnemonics of the set. SC140 DSP Core Reference Manual 5-31...
Page 212: Loop Timing
The memory space for interrupts is replicated on each task stack since any task can be interrupted. The interrupt functions can use the stack for subroutines, local variables, and so on. So each task stack must be increased by the size of the maximal interrupt memory use. 5-32 SC140 DSP Core Reference Manual...
Page 213: Sc140 Dual Stack Memory Use
As the core enters the exception working mode, the RTOS usually needs to save the current context by storing registers other than the SR and PC in the normal stack. For this purpose, specialized push and pop instructions (PUSHN/POPN) are provided that always access the normal stack, regardless of the mode. SC140 DSP Core Reference Manual 5-33...
Page 214: Stack Support Instructions
Any execution set that includes one or two push instructions increments the stack pointer by eight. In the case of a single push, a single operand is written to the memory while the adjacent memory location remains unchanged. 5-34 SC140 DSP Core Reference Manual...
Page 215: Shadow Stack Pointer Registers
When an NSP or ESP is written (by TFRA), then its shadow register automatically becomes invalid. In this situation, the first pop instruction takes an additional cycle. When a push/pop instruction is executed, then the shadow register of the active NSP or ESP becomes valid. SC140 DSP Core Reference Manual 5-35...
Page 216: Fast Return From Subroutines
The RTSTK instruction can be used to bypass the special logic that implements this fast RTS mechanism. This instruction retrieves the return address from the stack also when the RAS is valid. RTSTK is typically used when the return address from subroutine is explicitly changed in the stack. 5-36 SC140 DSP Core Reference Manual...
Page 217: Working Modes
This is the default state of the core after exiting the reset state. Refer to Section 5.8, “Exception Processing,” for a detailed description of the different exception types, and of the way an exception is serviced. SC140 DSP Core Reference Manual 5-37...
Page 218: Typical Working Mode Usage Scenarios
TRAP instruction, or an exception or external interrupt request occurs. When the working mode changes from Normal to Exception mode, EXP is set by the core, and the previous SR is pushed on the exception stack. 5-38 SC140 DSP Core Reference Manual...
Page 219: Single-Stack Rtos
TRAP instructions, or via an imprecise exception or interrupt request. It can also enter the Exception mode by explicitly setting the EXP in the SR (directly using an instruction or indirectly using RTE where in the restored SR EXP=1). Upon an exception, the following implicit actions occur: SC140 DSP Core Reference Manual 5-39...
Page 220 VBA + 0x00, since the TRAP instruction has an exception offset address of 0x00. If choosing to prepare the return values on the stack explicitly to perform this transition, the programmer should be aware that in Normal mode RTE uses the active stack (NSP). 5-40 SC140 DSP Core Reference Manual...
Page 221: Processing States
Table 5-16. Processing State Change Instructions Instruction Description DEBUG Enter debug state DEBUGEV Signal a debug event STOP Stop processing (lowest power stand-by) WAIT Wait for interrupt (low power stand-by) SC140 DSP Core Reference Manual 5-41...
Page 222: Processing State Transitions
5.7.2 Processing State Transitions The transitions between the states are summarized in the following figure. EXECUTION DEBUG RESET WAIT STOP Figure 5-10. Core State Diagram Table 5-17 describes the processing state transitions shown in Figure 5-10. 5-42 SC140 DSP Core Reference Manual...
Page 223: Execution State
The core remains in the reset state until the end of hardware reset. Upon leaving the reset state, the core enters the exception working mode, as part of the execution state, and program execution begins at a derivative-dependent program memory address. SC140 DSP Core Reference Manual 5-43...
Page 224: Debug State
Table 5-18 describes exit from Wait Process State, due to interrupt and NMI, under various core conditions. 1. i.e. IPL of the interrupt is greater than the core IPL, as determined by bits I2-I0 of the SR. See Table 5-18 for more information. 5-44 SC140 DSP Core Reference Manual...
Page 225: Stop Processing State
If no interrupt is pending, the core enters the execution state and executes the instruction following the STOP instruction that caused the entry into the stop state. SC140 DSP Core Reference Manual 5-45...
Page 226: Exception Processing
The second priority type, the interrupt priority level, determines whether a maskable external interrupt is taken or not. 5-46 SC140 DSP Core Reference Manual...
Page 227: Core-Pic Interface
2. The PSEQ in the core automatically ignores any interrupt request with an IPL lower than or equal to the interrupt mask level in the SR. NMIs and internal exceptions are serviced regardless of the current IPL. SC140 DSP Core Reference Manual 5-47...
Page 228: Interrupt Vector Address
Table 5-19 shows the exception vector address offsets. The last row in the table is for offsets from 0x200 to 0xFC0. These can be accessed by either the non-maskable interrupt or the (maskable) external interrupt, since the user-driven Interrupt Offset bus determines this address for either type. 5-48 SC140 DSP Core Reference Manual...
Page 229: Return From Exception Instructions
In such a case, the user should clear the RAS by performing, in the ISR that switches the tasks, a dummy jump to subroutine (JSR) and return (RTS). . SC140 DSP Core Reference Manual 5-49...
Page 230: Maskable Interrupts
VLES address of the first occurrence of the last exception type. For multiple events of the same type, only the first event will be sampled in PC_EXCP. For more information on the PC_EXCP register, Section 4.7.8, “PC of the Exception Execution Set (PC_EXCP).” 5-50 SC140 DSP Core Reference Manual...
Page 231: Illegal Exception
In particular, additional illegal events that occur between the first event and its illegal exception service routine will share the same exception. If an illegal SC140 DSP Core Reference Manual 5-51...
Page 232: Dalu Overflow
When the PSEQ acknowledges an exception request for service, the exception vector address is driven onto the program address bus. The core then enters exception mode, fetching instructions starting at the exception vector address. 5-52 SC140 DSP Core Reference Manual...
Page 233: Exception Mode Execution
ES3 is pushed as a return address to the stack. • 1 cycle is added, which is needed to push the return address to the stack. Else, if (ES1 is not JUMP) and (ES2 is JUMP): SC140 DSP Core Reference Manual 5-53...
Page 234 – The execution set from the target of the exception vector is executed after ES0, and the address of ES1 is pushed as a return address to the stack. – 3 cycles are added. 5-54 SC140 DSP Core Reference Manual...
Page 235: Flowchart For Exception Timing
Execute exception vector. Execute ES2. Is ES2 a JUMP? Store ES3 address. Add one cycle. Execute exception vector. Execute ES1. Store ES2 address. Add two cycles. Execute exception vector. Figure 5-12. Flowchart for Exception Timing SC140 DSP Core Reference Manual 5-55...
Page 236: Pipeline Example
ES1 and ES2 are not change-of-flow instructions. And, I1 is the first instruction at the exception vector address. The exception request is initiated in cycle 4. Table 5-21. Pipeline Example Instruction Cycle Operation Pre-fetch Fetch Decode push Address push Generation Execute push 5-56 SC140 DSP Core Reference Manual...
Page 237: Instruction Set Accelerator Plug-In
1. However, using the SIMD (single instruction, multiple data) approach, more complex configurations that enable dispatching an instruction to more than one ISAP at a time are possible. For details, see the Integration Guide. SC140 DSP Core Reference Manual 6-57...
Page 238: Isap - Sc140 Schematic Connection
The ISAP then drives or samples the data buses accordingly. The way the ISAP memory access is shared between the core and the ISAP is described in Section 6.4, “ISAP Memory Access.” 6-58 SC140 DSP Core Reference Manual...
Page 239: Multiple Isap
Further operation is similar to a single ISAP: The connections of the ISAPs with the data memory are not shown in Figure 6-2. Proper muxing should be implemented according to the same principle as shown in Figure 6-1. SC140 DSP Core Reference Manual 6-59...
Page 240: Isap Instructions And Instruction Encoding
The ISAP should not be designed with an AGU, leaving the addressing duties to the core. This allows the ISAP to enjoy the full addressing and modulo capabilities of the core AGU, and the ISAP design to concentrate on the specific ISAP specialty. 6-60 SC140 DSP Core Reference Manual...
Page 241: Isap-Core Register Transfers
A-275). When executed in parallel with an ISAP instruction, the core does not drive or sample the “Db” (DALU) register. This enables the core to perform data transfers between the C4 registers (D, R, N, B, M) and ISAP registers. SC140 DSP Core Reference Manual 6-61...
Page 242: Immediate Data Transfer To Isap Registers
The core does not take the number $1234 and place it in d0, but it takes the number $1234, and drives it on the core-ISAP register bus. In a complementary manner, the ISAP move_special instruction should only sample the data from the core-ISAP bus, and place it in the k0 ISAP register. 6-62 SC140 DSP Core Reference Manual...
Page 243: Core Assembly Syntax With An Isap
In this example, three parallel instructions are used: 1st - nop = a core instruction 2nd - {tsteq k0} = a fictional ISAP instruction (for illustration purposes only), written in the syntax of the appropriate ISAP. SC140 DSP Core Reference Manual 6-63...
Page 244: Working With Multiple Isaps
This method is preferred when multiple ISAP modules are used with the core, and are used interchangeably in the same code section. In the following example, the two ISAPs that are connected in parallel are a Floating Point ISAP (FP) and an Image Processing ISAP (IP): 6-64 SC140 DSP Core Reference Manual...
Page 245: An Example Of The Definition Flexibility Of An Isap
This example shows how flexible and powerful the ISAP can be, and demonstrates a MOVE instruction that includes other tasks in the same opcode: nop {permute_lsb_set.2l (r0)+,k0} abs d0 SC140 DSP Core Reference Manual 6-65...
Page 246: Conditional Execution
The move instructions inside the ISAP brackets translates into an implicit core MOVE instructions, each conditioned by a different IFc condition. Example 6-7. Conditional Execution Example 1 [ ift mac d0,d2,d4 mac d1,d3,d5 2 iff {alu_instruction k0,k1,k2 3 move_special.w k2,(r1)+} move.l (r0)+,r2] 6-66 SC140 DSP Core Reference Manual...
Page 247: Programming Rules
The ISAP’s pipeline should be coupled to the SC140 core, which means that instructions that perform data memory accesses or data processing should have similar pipeline behavior like respective SC140 core AGU or DALU instructions. For a description on the SC140 pipeline, see Chapter 5.1, “Pipeline.” SC140 DSP Core Reference Manual 6-67...
Page 248: Grouping Rules For Explicit Isap Instructions
In a manner similar to the one shown, the following rules are relevant also to implicit AGU instructions: G.G.5, G.P.1, G.P.4, G.P.5, G.P.6, A.1, A.2, A.4, T.1, SR.2, A.2a, A.5, A.6, D.7, A.1a. 6-68 SC140 DSP Core Reference Manual...
Page 249: Sequencing Rules For T Bit Update
T.2c: 2 VLES required between an ISAP instruction that updates the T bit and an AGU instruction conditioned by IFT/F. In addition, ISAP instructions that change the T bit or depend on it (via IFc) are subject to the same rules as are other core instructions: T.1, D.2, D.3. SC140 DSP Core Reference Manual 6-69...
Page 250 Programming Rules 6-70 SC140 DSP Core Reference Manual...
Page 251: Programming Rules
— Grouped instructions are placed on the same assembly source line, or on one or more lines surrounded by brackets [...]. 1. Semantics is the meaning of language. In this context, the function of instructions, the relationship between instructions in a VLES, and the relationship between VLES in a program. SC140 DSP Core Reference Manual...
Page 252 — If no carry-affecting instructions execute, the carry bit is not affected. • Even though the SC140 may execute instructions grouped in a VLES during different pipeline stages, the assembly source grouping for parallel instruction execution is enforced. SC140 DSP Core Reference Manual...
Page 253: Sc140 Pipeline Exposure
(highest word position) in its respective VLES encoding. This reordering conforms to the carry-update semantics described in Section 7.2, “VLES Grouping Semantics,” and is described in Section 5.2.5, “Instruction Reordering Within an Execution Set.” SC140 DSP Core Reference Manual...
Page 254: Sequencing Rules
A-19. 7.4.3.1 Register Names Some rules apply to selected registers — address, data, or program control. The rules specify the registers using the names given in Table A-3: Register Abbreviations on page A-3. SC140 DSP Core Reference Manual...
Page 255: B Register Aliasing
Update and address pre-calculation addressing modes. When a programming rule applies to only one operand type, it will be stated in the rule definition. If not stated, the rule applies to both address and data operands of the MOVE-like instruction. SC140 DSP Core Reference Manual...
Page 256: Agu Arithmetic Instructions
D. Example 7-2. Delayed COF Instructions BRAD BSRD CONTD JMPD JSRD RTED RTSD RTSTKD 7.4.9.1 Delay Slot A “delay slot” is the next sequential VLES after a VLES having a “delayed COF instruction.” SC140 DSP Core Reference Manual...
Page 257: Hardware Loops
Each loop n has one SA and one LA specified by the LOOPSTARTn and LOOPENDn directives, respectively. • Loops enter at SA and exit from LA, except for exits using loop control instructions: BREAK and CONT/CONTD. SC140 DSP Core Reference Manual...
Page 258: General Grouping Rules
This rule does not apply to prefix instructions listed in Table A-16: Prefix Instructions on page A-18 because they do not allocate execution units. Example 7-4 Too Many AGU Instructions bmtsts #$eb22,d5.h move.w r2,(r0)+ move.w r2,(r5) ;not allowed SC140 DSP Core Reference Manual...
Page 259 ;not allowed pop d1 tfra r0,sp ;not allowed tfra r0,sp tfra r1,osp ;allowed - writes different regs. • Multiple instructions that write different portions of the same register cannot be grouped in a VLES. SC140 DSP Core Reference Manual...
Page 260 De field popn Do field ;allowed ift push De field ifa push Do field ;allowed • Two mutually exclusive writes to the same register (except the PC register) can be grouped in a VLES. 7-10 SC140 DSP Core Reference Manual...
Page 261: Prefix Grouping Rules
Example 7-15. DALU Register Use Exceeds Four Times mac d2,d2,d2 add d2,d2,d3 ;not allowed - d2 used 5 times as a source 7.5.3 Prefix Grouping Rules The following rules only apply to prefix-grouped VLES. SC140 DSP Core Reference Manual 7-11...
Page 262: Prefix Instructions
Some absolute addresses or offsets • Bit mask instructions listed in Table A-16: Prefix Instructions on page A-18 • INSERT or EXTRACT/U instructions • Integer double precision instructions such as IMACxx, IMACxxxx, IMPYxx, IMPYxxxx and IMPY.W 7-12 SC140 DSP Core Reference Manual...
Page 263 The same Nn or Mn register can be used as a data source operand of a MOVE-like instruction only once in a VLES. For mutually exclusive IFc subgroups in a VLES, this rule applies independently to each subgroup. SC140 DSP Core Reference Manual 7-13...
Page 264 Example 7-22. IFA Subgroup Must Be Last Instructions ift add d0,d1,d2 iff add d3,d4,d5 iff inc d0 ;not allowed inc d0 ift add d0,d1,d2 ;not allowed ifa inc d0 ift add d0,d1,d2 ;not allowed ift add d0,d1,d2 ifa inc d0 ;allowed 7-14 SC140 DSP Core Reference Manual...
Page 265 Section 6.7.3, “Conditional Execution.” Example 7-24. ISAP instructions in same IFc group ift {isap_one} iff {isap_two} ;not allowed ift move.w d3,(r4) iff {move_special} {isap_two} ;allowed ift move.l d2,(r1) iff add d3,d4 {isap_ins} ;allowed SC140 DSP Core Reference Manual 7-15...
Page 266: Agu Rules
;use MCTL, allowed move.l d0,mctl ;change MCTL adda #$1234,r1,r8 ;no modifier mode, not allowed move.l d0,mctl ;change MCTL move.w (r0),d0 ;no update mode, allowed move.l d0,mctl ;change MCTL move.w (r8)+,d0 ;no modifier mode, allowed 7-16 SC140 DSP Core Reference Manual...
Page 267 2. Writing to Bn and Mn is covered by dynamic rule A.2a. 3. B and R aliasing is applicable for other rule exceptions as well. See Chapter 7.4.3.2, “B Register Aliasing,” for more details. SC140 DSP Core Reference Manual 7-17...
Page 268 VLES, this rule applies independently to each subgroup. Example 7-28. LCn Write to MOVE-like Use doen0 r0 move.l lc0,d0 ;not allowed doensh0 #5 push lc0 ;not allowed cont move.l lc1,d3 ;not allowed contd push lc2 ;not allowed 7-18 SC140 DSP Core Reference Manual...
Page 269: Delayed Cof Rules
7.5.5 Delayed COF Rules Rule D.1 The following instructions are not allowed in a delay slot: • COF instructions • STOP and WAIT • • DEBUG Example 7-30. Instructions in a Delay Slot jmpd r1 ;not allowed SC140 DSP Core Reference Manual 7-19...
Page 270 Core or ISAP instructions that write the SR register or affect status bits in SR cannot be grouped in a VLES with a RTE/RTED instruction. Example 7-32. RTE/D with SR Updates add d0,d1,d2 ;not allowed - affects the carry bit in SR {tsteq k0} ;not allowed - affects the T bit in SR 7-20 SC140 DSP Core Reference Manual...
Page 271 RTED, , and RTSTKD) instructions. This rule also applies to implicit SP register writes (push and pop instructions). Example 7-36. SP Use in Return Delay Slots rtsd tfra r0,sp ;not allowed rted tfra sp,r0 ;not allowed rtsd tfra r0,osp ;allowed rtstkd tfra osp,r0 ;allowed rtstkd pop d0 ;not allowed SC140 DSP Core Reference Manual 7-21...
Page 272: Status Bit Rules
Example 7-39. T Bit Update to IFT/IFF AGU Use tsteq d0 ift move.l r0,d1 ; not allowed tsteq d0 ift move.l r0,d1 ; allowed tsteq d0 ift mac d0,d1,d2 ; allowed tsteq d0 ift mac d0,d1,d2 ifa move.l r0,d1 ; allowed 7-22 SC140 DSP Core Reference Manual...
Page 273 {tsteq k0} ift move.l d1,d2 ; allowed Rule SR.2 At least two VLES are required between a MOVE-like instruction that writes the SR register and an instruction affected by a status bit in SR. SC140 DSP Core Reference Manual 7-23...
Page 274 The assembler-mapped instruction CLR Dn is never affected by SR status bits, even though it is implemented as SUB Da,Da,Dn. Therefore, this rule applies to the SUB instruction, but not to CLR (SUB Da,Da,Dn is taken as CLR in this context). 7-24 SC140 DSP Core Reference Manual...
Page 275 ;change SR clr d0 ;allowed, clear not effected by SR move.l d1,sr ;change SR sub d1,d2,d3 ;not allowed, sub effected by S0,S1 move.l d1,sr ;change SR sub d1,d1,d3 ;allowed, this is a CLR SC140 DSP Core Reference Manual 7-25...
Page 276 The assembler-mapped instruction CLR Dn never affects the DOVF status bit, even though it is implemented as SUB Da,Da,Dn. Therefore, this rule applies to the SUB instruction, but not to CLR (SUB Da,Da,Dn is taken as CLR in this context). 7-26 SC140 DSP Core Reference Manual...
Page 277 ; Allowed (OVE not changed) move.l #$100000,sr mac d0,d1,d2 ; Not allowed move.l d0,sr mac d0,d1,d2 ; Not allowed pop sr mac d0,d1,d2 ; Not allowed rted mac d0,d1,d2 ; Not allowed SC140 DSP Core Reference Manual 7-27...
Page 278: Loop Nesting Rules
;not allowed skipls _dest bmtsts #4,sr.h ;not allowed 7.5.7 Loop Nesting Rules Rule L.N.1 Nested loops cannot have the same LA. Example 7-48. Nested Loops with the Same LA move.w r3,(r4) loopend1 loopend0 ;not allowed 7-28 SC140 DSP Core Reference Manual...
Page 279 LOOPSTARTn directive, or a DOEN instruction with any index between the DOENSHn instruction and its respective LOOPSTARTn directive. Example 7-50. Nested DOENn/DOENSHn Instructions count2 equ 5 move.w #count2,d6 dosetup0 label2 doen0 doen1 ; not allowed loopstart0 doen1 doen1 ; allowed loopstart1 SC140 DSP Core Reference Manual 7-29...
Page 280 ;problem becomes apparent here loopstart3 loopend3 Example 7-53. Changing a loop type doensh0 #3 doen0 #3 ; not allowed to change loop type dosetup0 _loop_start _loop_start loopstart0 move.l #0,d0 move.l #1,d0 move.l #2,d0 loopend0 7-30 SC140 DSP Core Reference Manual...
Page 281: Loop La Rules
A DOENn or MOVE-like instruction that writes a LCn register is not allowed at LA-2, LA-1, or LA of the same long loop n. Example 7-55. LCn Write at the End of Long Loop n doen1 #5 ;not allowed move.w d3,(r1)+ loopend1 SC140 DSP Core Reference Manual 7-31...
Page 282 Example 7-57. Short Loop LA at the End of a Long Loop dosetup0 label1 doen0 #count1 move.w #num,d1 loopstart0 label1 inc d1 doensh1 #count2 move.w #num1,d2 loopstart1 label2 inc d2 impyuu d1,d2,d3 ;not allowed loopend1 loopend0 7-32 SC140 DSP Core Reference Manual...
Page 283: Loop Sequencing Rules
DOENn Dn: four VLES (data register) • MOVE-like instruction that writes a LCn register: four VLES Example 7-59. LCn Write at the End of Long Loop n move.w #3,d8 dosetup1 label1 doen1 d8 ;not allowed loopstart1 label1 inc loopend1 SC140 DSP Core Reference Manual 7-33...
Page 284 ;not allowed loopend1 Rule L.D.6 A MOVE-like instruction that writes a SAn register is not allowed at (LA-3), (LA-2), (LA-1), and LA of the same long loop n. 7-34 SC140 DSP Core Reference Manual...
Page 285 At least one VLES is required between a MOVE-like instruction that reads a LCn register and SA of the same short loop n. Example 7-64. LCn Read at the Start of Short Loop n doensh0 #$10 push ;not allowed loopstart0 loopend0 doensh0 #$10 push ;allowed loopstart0 loopend0 SC140 DSP Core Reference Manual 7-35...
Page 286: Loop Cof Rules
A Bc or Jc instruction is not allowed at SA-1 of a short loop. Example 7-67. Bc/Jc at SA-1 of a Short Loop cmpgt d4,d3 iff doensh3 #count2 bt _dest ;SA-1, not allowed loopstart3 inc d2 loopend3 _dest inc d2 7-36 SC140 DSP Core Reference Manual...
Page 287 A Bc or Jc instruction is not allowed at LA-3 of a long loop. Example 7-68. Bc/Jc at LA-3 of a Long Loop dosetup1 label7 move.w #0,d1 doen1 loopstart1 label7 inc d1 bf label6 ;LA-3, not allowed inc d2 inc d3 inc d4 loopend1 SC140 DSP Core Reference Manual 7-37...
Page 288 #6 loopstart2 label1 cont next ;not allowed inc d0 dosetup3 label2 doen3 #5 loopstart3 label2 inc d1 next inc d2 inc d3 inc d4 inc d5 loopend3 loopend2 7-38 SC140 DSP Core Reference Manual...
Page 289 Example 7-71. Subroutine Call to End of Loops dosetup0 label1 doen0 d1 loopstart0 label1 nop jsr label2 ;not allowed inca r1 label2 inca r7 ;LA-2 add d1,d2,d3 ;LA-1 move.w d3,(r0) loopend0 SC140 DSP Core Reference Manual 7-39...
Page 290: General Looping Rules
At least one VLES is required between a MOVE-like instruction that reads the SR register and SA of any short loop. Example 7-75. SR Read to SA of Any Short Loop doensh0 #$10 push sr ;not allowed loopstart0 inc d0 loopend0 7-40 SC140 DSP Core Reference Manual...
Page 291: Dynamic Programming Rules
MCTL. Example 7-77. Bn, Mn Write to AGU Use move.l #$000000f, MCTL ; r0 only has modulo addressing move.l d0,b0 move.w (r0)+,d1 ; Not allowed pop d0,m1 adda r9,r1 ; Allowed SC140 DSP Core Reference Manual 7-41...
Page 292: Memory Access Rules
VLES having the RTED, RTSD or RTSTKD instruction. Example 7-80. Memory Write to Stack in a Return Delay Slot tfra sp,r0 move.l d1,(r0-8) ;allowed rtsd move.l d2,(r0-8) ;not allowed 7-42 SC140 DSP Core Reference Manual...
Page 293: Ras Rules
LFn state when these instructions execute, the simulator detects this programming rule. Good loop programming practices can ensure that rule L.N.6 is enforced. Rule L.N.6 Loop COF instructions (BREAK, CONT, CONTD, and SKIPLS) cannot be used if all loops are disabled. SC140 DSP Core Reference Manual 7-43...
Page 294: Rule Detection Across Cof Boundaries
COF destination. However, this cycle barrier is reduced when the instructions are grouped in a VLES with the COF instruction (or its delay slot). The relevant cycle-based rules that the simulator detects across COF boundaries are: • • • A.2a 7-44 SC140 DSP Core Reference Manual...
Page 295: Vles-Based Cof Rules
_des2 ift tfra r0,r1 ; Allowed bt _des3 cmpeq d0,d1 _des3 ift tfra r0,r1 ; Not allowed jsrd _des4 cmpeq d0,d1 _des4 ift tfra r0,r1 ; Allowed (1 extra VLES calculated between cmpeq and ift) SC140 DSP Core Reference Manual 7-45...
Page 296: Rule Detection Across Exception Boundaries
; ISR Start move #$00000004,sr ; Not allowed Rule SR.6 The following instructions are not allowed in the first two VLES of an exception service routine: • DOENn/DOENSHn • CONT/CONTD • BREAK • SKIPLS 7-46 SC140 DSP Core Reference Manual...
Page 297 ; ISR Start adda #$1234,r8,r1 ;use MCTL, not allowed ; ISR Start adda #$1234,r1,r8 ;no modifier mode, allowed ; ISR Start move.w (r0),d0 ;no update mode, allowed ; ISR Start move.w (r8)+,d0 ;no modifier mode, allowed SC140 DSP Core Reference Manual 7-47...
Page 298: Programming Guidelines
In order to create non-interruptible sequences, the user should use other mechanisms such as the BMTSET.W instruction or encapsulating the code with the DI and EI instructions. Complying with this rule will help to insure compatibility with future StarCore architectures. 7-48 SC140 DSP Core Reference Manual...
Page 299: Rules Not Detected Across Cof Boundaries
COF destination address. • Use symbolic data labels (not absolute addresses). Use symbolic labels and symbol arithmetic for offsets into data structures. Let the assembler resolve the label to a data element address. SC140 DSP Core Reference Manual 7-49...
Page 300: Binary Code Practices
Do not write self-modifying code (replacing portions of an application binary at run-time). It cannot be checked for errors by the assembler. It is also difficult to debug, and may not be compatible with future processor implementations. 7-50 SC140 DSP Core Reference Manual...
Page 301: Software Development Practices
LPMARKA and LPMARKB instructions, and 2) how the LPMARK bits encoded in the prefix are used by the simulator to detect some SC140 programming rules. 7.8.1 LPMARK Instruction Type LPMARK is classified as a prefix instruction type for all SC140 programming rules. SC140 DSP Core Reference Manual 7-51...
Page 302: Static Programming Rules
“active loop”. This definition is dynamic and follows the SC140 loop state machine. The SC140 loop state machine and simulator determine the “active loop” from the LFn bits in SR when a VLES having an LPMARK bit set is executed. 7-52 SC140 DSP Core Reference Manual...
Page 303: Loop Nesting Rules
Example 7-92. Instructions at the End of Long Loops move.w #count2,d6 dosetup0 label2 doen0 move.w #1,d1 move.w #2,d2 move.w #3,d3 move.w #4,d4 label2 inc d1 inc d2 inc d3 {lpmarkb set} inc d4 wait ;not allowed SC140 DSP Core Reference Manual 7-53...
Page 304 #count2 move.w #num,d2 doen1 #5 {lpmarka set} ;not allowed LPMARK Rule L.L.5 A MOVE-like instruction that writes the SR register is not allowed at LPB-2, LPB-1, LPB, LPB+1, or LPB+2 of a long loop. 7-54 SC140 DSP Core Reference Manual...
Page 305: Loop Sequencing Rules
{lpmarkb set} inc d1 inc d0 LPMARK Rule L.D.8 + L.D.9 At least one VLES is required between a MOVE-like instruction that reads the active LCn register and LPA or LPB of a loop. SC140 DSP Core Reference Manual 7-55...
Page 306: Loop Cof Rules
#4,d4 label2 inc d1 move.l lc1,d0 ;allowed inc d2 {lpmarkb set} inc d3 inc d4 7.8.3.5 Loop COF Rules LPMARK Rule L.C.2 COF instructions are not allowed at LPB of a long loop. 7-56 SC140 DSP Core Reference Manual...
Page 307 #count2 bt _dest ;not allowed inc d2 {lpmarka set} _dest inc d2 dosetup1 label7 move.w #0,d1 doen1 move.w #10,d2 label7 inc d1 bf label6 ;not allowed inc d2 {lpmarkb set} inc d3 inc d4 SC140 DSP Core Reference Manual 7-57...
Page 308 A BSR, BSRD, JSR, or JSRD instruction cannot have a COF destination that is at LPA or LPB of a loop. Example 7-101. Subroutine Call to End of Loops dosetup0 label1 doen0 d1 label1 nop jsr label2 ;not allowed inca r1 label2 inca r7 {lpmarkb set};LA-2 add d1,d2,d3 ;LA-1 move.w d3,(r0) 7-58 SC140 DSP Core Reference Manual...
Page 309: General Looping Rules
7.8.4 LPMARK Programming Guidelines The rules in this section cannot be detected by the simulator from its execution trace. The following rules must be detected by the programmer, and can be avoided by good programming practices. SC140 DSP Core Reference Manual 7-59...
Page 310: Nop Definition
N NOPs in the source code has a size of N words. It is implemented by a standalone 1W NOP prefix having the VLES size in the aaa field followed by N-1 embedded 1W NOP prefixes having aaa=0. This is the only guaranteed way to pad N consecutive words. 7-60 SC140 DSP Core Reference Manual...
Page 311: Grouping Examples
Assume there are N NOP instructions in the source VLES (including PADs added by the FALIGN directive). 1. If a baseline VLES does not require a prefix, the first source NOP is encoded as a 1W VLES prefix. For example: [INC D0NOP] is encoded as: [1W prefix, INC] SC140 DSP Core Reference Manual 7-61...
Page 312 6. If a baseline VLES has a NOP with other instructions in a conditional subgroup, a 1W embedded NOP is encoded for each source NOP in either subgroup. For example: [IFT CLR D8IFF INC D1 IFF NOP] is encoded as: 7-62 SC140 DSP Core Reference Manual...
Page 313 7. If a baseline VLES has multiple NOPs in a conditional subgroup, a 1W embedded NOP is encoded for each source NOP. For example: [IFT CLR D0IFT NOP IFT NOP] is encoded as: [1W IFT prefix, CLR, NOP, NOP] SC140 DSP Core Reference Manual 7-63...
Page 314 NOP Definition 7-64 SC140 DSP Core Reference Manual...
Page 315: Sc140 Dsp Core Instruction Set
This extensive range of instruction capabilities also provides a very powerful assembly language for DSP algorithms and general-purpose computing. Certain programming rules apply regarding the ability to group instructions that activate the various units, because of their use of shared resources. SC140 DSP Core Reference Manual...
Page 316: Conventions
However, note that if this is used in assembler code, the contents will be understood as ISAP instructions. [b:a] Bit range a to b in a register or memory Bit number a in a register or memory SC140 DSP Core Reference Manual...
Page 317: Operations Syntax
Stack pointer registers: normal (NSP) and exception (ESP) Program counter Status register MCTL Modifier control register SA0-SA3 Start address registers LC0-LC3 Loop counter registers B0-B7 Modulo base registers N0-N3 Offset registers M0-M3 Modulo registers Other stack pointer SC140 DSP Core Reference Manual...
Page 318: Brackets As Isap Indicators
The ranges shown in the brackets are always for the source code addressing. The ranges may or may not reflect the number of bits used in the encoding, depending on whether a left shift is applied to the encoded value. SC140 DSP Core Reference Manual...
Page 319: Addressing Mode Notation
Notation in Instruction Field Indexed by offset in N0 (Rn + N0) Post decrement (Rn)– No update (Rn) Post increment (Rn)+ Note: Rn is taken from the Rn (RRR) table found in the instruction definition. SC140 DSP Core Reference Manual...
Page 320: Data Representation In Memory For The Examples
20-bit signed PC relative displacement (>label) If the field was written out in the encoding table, it would appear as follows: BSR >label A15 A14 A13 a19 a18 a17 A12 A11 A10 A9 SC140 DSP Core Reference Manual...
Page 321: Prefix Word Encoding
Note: Use of a prefix reduces the space available for instructions in the eight-word execution set by the size of the prefix. For example, if an instruction that references a high-bank register causes the assembler to generate a two-word prefix,only six words are left available in that execution set for instructions. SC140 DSP Core Reference Manual...
Page 322: One-Word Low Register Prefix
In case of a loop with more than three execution sets, the lpmarkA bit is set in the prefix of the execution set which is at _last only if there are any SKIPLS, BREAK, CONT, CONTD to _last, or to _last-1. SC140 DSP Core Reference Manual...
Page 323: Two-Word Prefix
In the case of a loop with three or more execution sets, the lpmarkB bit is a one in the execution set that is two before the last execution set in the loop. SC140 DSP Core Reference Manual...
Page 324 MAX D8,D4. eee: The same as EEE, but for DALU execution unit 1. BBB: The same as EEE, but for DALU execution unit 2. bbb: The same as EEE, but for DALU execution unit 3. A-10 SC140 DSP Core Reference Manual...
Page 325 Note that Rr register in (Rn+Rr) addressing mode, is limited to R0-R7 and thus not effected by both H and h bits. The same as Hh, but for AGU execution unit 1. Note the special position of the T bit (bit 8 in the second word). SC140 DSP Core Reference Manual A-11...
Page 326: Instruction Types
— Loop change-of-flow instructions are also listed in Table A-14 and are described in Section 5.3.2, “Change-Of-Flow Instruction Timing,” on page 5-17. • Program control instructions are listed in Table A-15 and described in Section 5.7.1, “Processing State Change Instructions,” on page 5-41. A-12 SC140 DSP Core Reference Manual...
Page 327 Multiply-accumulate unsigned fraction and unsigned fraction Transfer maximum signed value MAX2 Transfer two 16-bit maximum signed values MAX2VIT Special MAX2 version for Viterbi kernel MAXM Transfer maximum magnitude value Transfer minimum signed value Multiply signed fractions SC140 DSP Core Reference Manual A-13...
Page 328: Dalu Logical Instructions (Bfu
Extract unsigned bit field INSERT Insert bit field LSLL Multi-bit logical shift left Logical shift right by one bit LSRR Multi-bit logical shift right LSRW Word logical shift right (16-bit shift) One’s complement (inversion) Logical inclusive OR A-14 SC140 DSP Core Reference Manual...
Page 329 Move the “other” stack pointer to/from a register, inversely defined by the exception mode TSTEQA.L Test for equal TSTEQA.W Test for equal on lower 16 bits TSTGEA Test for greater than or equal TSTGTA Test for greater than ZXTA.B Zero extend byte ZXTA.W Zero extend word SC140 DSP Core Reference Manual A-15...
Page 330: Agu Move Instructions
POPN Pop a register from the software stack using the normal stack pointer PUSH Push a register onto the software stack PUSHN Push a register onto the software stack using the normal stack pointer A-16 SC140 DSP Core Reference Manual...
Page 331: Agu Bit-Mask Instructions (Bmu
Branch if true Branch if true (delayed) Jump if false Jump if false (delayed) Jump JMPD Jump (delayed) Jump to subroutine JSRD Jump to subroutine (delayed) Jump if true Jump if true (delayed) Return from exception SC140 DSP Core Reference Manual A-17...
Page 332 Description Execute current execution set or subgroup unconditionally Execute current execution set or subgroup if the T bit is clear Execute current execution set or subgroup if the T bit is set No operation A-18 SC140 DSP Core Reference Manual...
Page 333: A.2 Instructions
Instruction Formats and Opcodes section. A field contains a table of registers or the definition of an immediate value, an absolute address displacement/offset, or an absolute address. A table of registers lists single register groups, register pair groups, address offset/post increment definition groups, or register quad groups. SC140 DSP Core Reference Manual A-19...
Page 334 (SR [SM] = 1), clears the Ln bit in the destination register. Example abs d0 Register/Memory Address Before After $00E0 0000 L0:D0 $0:FF FFFF FFF6 $0:00 0000 000A $0000 0000 $FFF6 = -10, $000A = 10 A-20 SC140 DSP Core Reference Manual...
Page 335 1 0 0 1 F F F 1 1 0 0 1 1 0 ABS Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-21...
Page 336 ;add with the carry bit Register/Memory Address Before After $FF 8000 0008 L1:D1 $0:$FF 8000 0005 $0:$FF 0000 000D $00E4 0000 $00E4 0001 $00 0000 0005 L5:D5 $0:$00 0000 0001 $0:$00 0000 0007 $00E4 00001 $00E0 0000 A-22 SC140 DSP Core Reference Manual...
Page 337 1 0 1 1 e e 0 1 1 1 1 0 1 0 ADC Dc,Dd Note: ** indicates serial grouping encoding. Instruction Fields Dc,Dd Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-23...
Page 338 Ln bit in the destination register. If in arithmetic saturation mode (SR [SM] = 1), clears the Ln bit in the destination register. Example 1 add d0,d1,d2 Register/Memory Address Before After $00E0 0000 $00 0000 0005 $00 0000 0002 A-24 SC140 DSP Core Reference Manual...
Page 339 1 1 1 0 F F F 1 0 ADD #u5,Dn 1 0 1 1 F F F 1 0 ADD Da,Db,Dn 1 0 0 0 F F F 1 1 0 0 0 ADD Da,Da,Dn Note: ** indicates serial grouping encoding. SC140 DSP Core Reference Manual A-25...
Page 340 D7,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. 5-bit unsigned immediate data iiiii A-26 SC140 DSP Core Reference Manual...
Page 341 Register/Memory Address Before After $00 1100 1100 L1:D1 $0:$00 2200 3300 $0:$00 3300 4400 Example 2 add2 d0,d1 Register/Memory Address Before After $00 1101 F011 L1:D1 $0:$00 0020 2002 $0:$00 1121 1013 SC140 DSP Core Reference Manual A-27...
Page 342 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-28 SC140 DSP Core Reference Manual...
Page 343 Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the instruction is not affected by MCTL. Status and Conditions Changed by Instruction None. SC140 DSP Core Reference Manual A-29...
Page 344 1 0 0 1 1 1 0 R R R R 0 0 0 1 ADDA rx,Rx Instruction Fields Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-30 SC140 DSP Core Reference Manual...
Page 345 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. iiiii 5-bit unsigned immediate data #s16 iiiiiiiiiiiiiiii 16-bit signed immediate data SC140 DSP Core Reference Manual A-31...
Page 346 MCTL. Example addl1a r0,r1 Register/Memory Address Before After MCTL $0000 0000 $0000 0055 $0000 0011 $0000 00BB In binary: 0101 0101 R0 shifted left 1010 1010 0001 0001 1011 1011 A-32 SC140 DSP Core Reference Manual...
Page 347 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-33...
Page 348 Status and Conditions Changed by Instruction None. Example addl2a r0,r1 Register/Memory Address Before After MCTL $0000 0000 $0000 0055 $0000 0011 $0000 0165 In binary: 0101 0101 R0 shifted left two 1 0101 0101 0001 0001 1 0110 0101 A-34 SC140 DSP Core Reference Manual...
Page 349 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-35...
Page 350 $FF FFFF CA3E L2:D2 $0:$FF FFFF 947C $00E0 0000 $00E0 0000 $0000 0000 An add with a carry allowed would result in setting the carry bit as a result of an overflow from bit 39. A-36 SC140 DSP Core Reference Manual...
Page 351 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. #s16 iiiiiiiiiiiiiiii 16-bit signed immediate data SC140 DSP Core Reference Manual A-37...
Page 352 (SR [SM] = 1), clears the Ln bit in the destination register. Example adr d3,d4 Register/Memory Address Before After $00 0034 A216 L4:D4 $0:$00 2000 0000 $0:$00 2035 0000 $00E0 0000 $0000 0000 A-38 SC140 DSP Core Reference Manual...
Page 353 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-39...
Page 354: And
AND Da,Dn Performs a bitwise AND on the contents of two source data registers (Da, Dn) and stores the result in the destination (second) data register (Dn). Status and Conditions that Affect Instruction None. A-40 SC140 DSP Core Reference Manual...
Page 355 #$ff2e0000,d2,d1 Register/Memory Address Before After immediate $FF FF2E 0000 $F0 27A6 98FB L1:D1 $0:$F0 2726 0000 Note: The value of the immediate $ff2e0000 is extended to $ffff2e0000 before the AND operation with D2. SC140 DSP Core Reference Manual A-41...
Page 356 This instruction can specify D8-D15 as operands by using a prefix. #0(u16) 0000000000000000 16-bit unsigned immediate data in lower word, iiiiiiiiiiiiiiii upper word zeroed #(u16)$0000 iiiiiiiiiiiiiiii 16-bit unsigned immediate data in upper word, 0000000000000000 lower word zeroed #u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data A-42 SC140 DSP Core Reference Manual...
Page 357 Clears the Ln bit in the destination register. Example and #$a70e,d1.h Register/Memory Address Before After immediate $A70E D1.H $57AF $070E In binary, $A70E 1010 0111 0000 1110 $57AF 0101 0111 1010 1111 and = $070E 0000 0111 0000 1110 SC140 DSP Core Reference Manual A-43...
Page 358 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a a prefix prefix. #u16 ~iiiiiiiiiiiiiiii One’s complement of 16-bit unsigned immediate data A-44 SC140 DSP Core Reference Manual...
Page 359 Performs a bitwise AND on a 16-bit unsigned immediate value and the contents of a memory address, pointed to by a 15-bit signed offset added to SP. Stores the result in the same memory address. Note: This instruction is assembler-mapped to BMCLR.W #~u16,(SP+s16). SC140 DSP Core Reference Manual A-45...
Page 360 Status and Conditions Changed by Instruction None. Example and.w #$54a1,(r7) Register/Memory Address Before After immediate $54A1 ($50) $15AF $14A1 In binary, $54A1 0101 0100 1010 0001 $15AF 0001 0101 1010 1111 and = $14A1 0001 0100 1010 0001 A-46 SC140 DSP Core Reference Manual...
Page 361 This instruction can specify R8-R15 as operands by using a high register prefix. 16-bit unsigned absolute address AAAAAAAAAAAAAAAA #u16 One’s complement of unsigned 16-bit ~iiiiiiiiiiiiiiii immediate data Unsigned 5-bit SP address offset AAAAA0 Signed 16-bit SP address offset AAAAAAAAAAAAAAAA SC140 DSP Core Reference Manual A-47...
Page 362: Ln Bit Calculation
Set if the result cannot be represented in 40 bits, or if the result saturates to 32 bits in arithmetic saturation mode. Example asl d0,d1 Register/Memory Address Before After $ff f001 0001 L1:D1 $0:$ff e002 0002 A-48 SC140 DSP Core Reference Manual...
Page 363 Data Register Pairs D1,D1 D3,D3 D5,D5 D7,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-49...
Page 364: Asl2A
AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-50 SC140 DSP Core Reference Manual...
Page 365: Asla
AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-51...
Page 366: Asll
If shifting right, the MSB of the source is copied into the vacated positions, creating a sign-extension. Da[6:0] > 0 Da[6:0] < 0 Status and Conditions that Affect Instruction None. A-52 SC140 DSP Core Reference Manual...
Page 367 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 0 SC140 DSP Core Reference Manual...
Page 368 Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. 5-bit unsigned immediate data iiiii A-54 SC140 DSP Core Reference Manual...
Page 369: Aslw
0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC140 DSP Core Reference Manual A-55...
Page 370 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-56 SC140 DSP Core Reference Manual...
Page 371: Asr
Set if the result cannot be represented in 40 bits, or if the result saturates to 32 bits in arithmetic saturation mode. Example asr d5,d3 Register/Memory Address Before After $00 0000 7903 L3:D3 $0:$00 0000 3C81 SC140 DSP Core Reference Manual A-57...
Page 372 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-58 SC140 DSP Core Reference Manual...
Page 373: Asra
RRRR AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-59...
Page 374: Asrr
If shifting right, the MSB is copied into the vacated positions. If shifting left, the vacated positions to the right are zero-filled. N is obtained from Da[6:0]. Da[6:0] > 0 Da[6:0] < 0 Status and Conditions that Affect Instruction None. A-60 SC140 DSP Core Reference Manual...
Page 375 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 0 0 0 0 SC140 DSP Core Reference Manual...
Page 376 Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. 5-bit unsigned immediate data iiiii A-62 SC140 DSP Core Reference Manual...
Page 377 Da[15] is stored in the carry bit. Clears the Ln bit in the destination register. Example asrw d5,d0 Register/Memory Address Before After $80 1234 8765 L0:D0 $0:$00 0000 0000 $0:$ff ff80 1234 $00E0 0000 $00E0 0001 SC140 DSP Core Reference Manual A-63...
Page 378 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-64 SC140 DSP Core Reference Manual...
Page 379 Skipped over. - - - - Skipped over. - - - - Skipped over. - - - - Execution continues here at lbl. lbl move.w #$16,d4 Register/Memory Address Before After $00E4 0000 $0000 $0029 SC140 DSP Core Reference Manual A-65...
Page 380 Note 1: If the branch is not taken, it uses 1 cycle. If the branch is taken, it uses 4 cycles. Instruction Fields displacement (<label) 8-bit signed PC relative displacement AAAAAAAA0 displacement aaaaaAAAAAAAAAAAAAA 20-bit signed PC relative displacement (>label) A-66 SC140 DSP Core Reference Manual...
Page 381 #$47,d2 Skipped over. - - - - Skipped over. - - - - Skipped over. - - - - Execution continues here at lbl. lbl move.w #$1A,d4 Register/Memory Address Before After $00E0 0000 SC140 DSP Core Reference Manual A-67...
Page 382 The cycle count for this instruction cannot be less than 1 cycle. Instruction Fields displacement AAAAAAAA0 8-bit signed PC relative displacement (<label) displacement 20-bit signed PC relative displacement aaaaaAAAAAAAAAAAAAA (>label) A-68 SC140 DSP Core Reference Manual...
Page 383: Bit Mask
Inverts selected bits in the contents of the LP of a data or address register (DR). Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] Determines execution working mode for instructions that have these registers as an operand. SC140 DSP Core Reference Manual A-69...
Page 384 Data/Address Register 0000 0100 1000 1100 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. A-70 SC140 DSP Core Reference Manual...
Page 385 BMCHG.W #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii SC140 DSP Core Reference Manual A-71...
Page 386: Bmchg.w
Register Address Bit Name Description SR[18] Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None. A-72 SC140 DSP Core Reference Manual...
Page 387 Instruction Fields Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. AAAAAAAAAAAAAAAA 16-bit unsigned absolute address #u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data 5-bit unsigned SP address offset AAAAA0 SC140 DSP Core Reference Manual A-73...
Page 388 BMCHG.W AAAAAAAAAAAAAAAA 16-bit signed SP address offset A-74 SC140 DSP Core Reference Manual...
Page 389: Bmclr
Clears selected bits in the LP contents of a data or address register (DR). Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] Determines execution working mode for instructions that have these registers as an operand. SC140 DSP Core Reference Manual A-75...
Page 390 Data/Address Register 0000 0100 1000 1100 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. A-76 SC140 DSP Core Reference Manual...
Page 391 BMCLR #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii SC140 DSP Core Reference Manual A-77...
Page 392: Bmclr.w
Register Address Bit Name Description SR[18] Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None. A-78 SC140 DSP Core Reference Manual...
Page 393 This instruction can specify R8-R15 as operands by using a high register prefix. 16-bit unsigned absolute address AAAAAAAAAAAAAAAA #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii 5-bit unsigned SP address offset AAAAA0 16-bit signed SP address offset AAAAAAAAAAAAAAAA SC140 DSP Core Reference Manual A-79...
Page 394: Bmset
SR[18] Determines execution working mode for instructions that have these registers as an operand. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination register. Example A-80 SC140 DSP Core Reference Manual...
Page 395 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. #u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data SC140 DSP Core Reference Manual A-81...
Page 396: Bmset.w
Register Address Bit Name Description SR[18] Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None. A-82 SC140 DSP Core Reference Manual...
Page 397 This instruction can specify R8-R15 as operands by using a high register prefix. AAAAAAAAAAAAAAAA 16-bit unsigned absolute address #u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data AAAAA0 5-bit unsigned SP address offset 16-bit signed SP address offset AAAAAAAAAAAAAAAA SC140 DSP Core Reference Manual A-83...
Page 398: Bmtset
Set if all the bits selected by the mask were set, cleared otherwise. Clears the Ln bit in the destination data register. Example 1 bmtset #$111f,d1.l Register/Memory Address Before After $00E4 0000 $00E4 0000 immediate $111F $00 1234 5678 $00 1234 577F A-84 SC140 DSP Core Reference Manual...
Page 399 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii SC140 DSP Core Reference Manual A-85...
Page 400: Bmtset.w
Tests and sets selected bits in the contents of a memory address pointed to by an address register (Rn). BMTSET.W #u16,(a16) Tests and sets selected bits in the contents of a memory address pointed to by an absolute 16-bit address. A-86 SC140 DSP Core Reference Manual...
Page 401 Set if all the bits selected by the mask are set, or the memory access fails; cleared otherwise. Example bmtset.w #$4328,($c) Register/Memory Address Before After immediate $4238 ($C) $5678 $5678 $00E4 0000 $00E4 0002 SC140 DSP Core Reference Manual A-87...
Page 402 This instruction can specify R8-R15 as operands by using a high register prefix. 16-bit unsigned absolute address AAAAAAAAAAAAAAAA #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii 5-bit unsigned SP address offset AAAAA0 16-bit signed SP address offset AAAAAAAAAAAAAAAA A-88 SC140 DSP Core Reference Manual...
Page 403: Bmtstc
Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] Set if all the bits selected by the mask are clear, cleared otherwise. Example bmtstc #$8a59,d7.h Register/Memory Address Before After immediate $8A590000 SC140 DSP Core Reference Manual A-89...
Page 404 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii A-90 SC140 DSP Core Reference Manual...
Page 405: Bmtstc.w
Tests selected bits in the contents of a memory address pointed to by an address register (Rn). BMTSTC.W #u16,(a16) Tests selected bits in the contents of a memory address pointed to by an absolute 16-bit address. SC140 DSP Core Reference Manual A-91...
Page 406 Set if all the bits selected by the mask are clear, cleared otherwise. Example bmtstc.w #$8A59,(r0) Register/Memory Address Before After immediate $8A59 $0000 0002 $0000 0002 ($0002) $0000 24A6 $0000 24A6 $00E4 0000 $00E4 0002 $24A6 --0010 0100 1010 0110 mask $8A59 --1000 1010 0101 1001 A-92 SC140 DSP Core Reference Manual...
Page 407 This instruction can specify R8-R15 as operands by using a high register prefix. 16-bit unsigned absolute address AAAAAAAAAAAAAAAA #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii 5-bit unsigned SP address offset AAAAA0 16-bit signed SP address offset AAAAAAAAAAAAAAAA SC140 DSP Core Reference Manual A-93...
Page 408: Bmtsts
Tests selected bits in the LP contents of a data or address register (DR). Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] Set if all the bits selected by the mask are set, cleared otherwise. A-94 SC140 DSP Core Reference Manual...
Page 409 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii SC140 DSP Core Reference Manual A-95...
Page 410: Bmtsts.w
Tests selected bits in the contents of a memory address pointed to by an address register (Rn). BMTSTS.W #u16,(a16) Tests selected bits in the contents of a memory address pointed to by an absolute 16-bit address. A-96 SC140 DSP Core Reference Manual...
Page 411 Set if all the selected bits in the mask are set, or the memory access fails; cleared otherwise. Example bmtsts.w #$0428,(r0) Register/Memory Address Before After immediate $0428 (r0) $16FC $16FC $00E4 0000 $00E4 0002 In binary, $0428 0000 0100 0010 1000 $16FC 0001 0110 1111 1100 SC140 DSP Core Reference Manual A-97...
Page 412 This instruction can specify R8-R15 as operands by using a high register prefix. 16-bit unsigned absolute address AAAAAAAAAAAAAAAA #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii 5-bit unsigned SP address offset AAAAA0 16-bit signed SP address offset AAAAAAAAAAAAAAAA A-98 SC140 DSP Core Reference Manual...
Page 413: Bra
≤ (<label [–2 , W]) or a long branch (>label [–2 , W and 2 displacement < 2 , W]). Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction None. SC140 DSP Core Reference Manual A-99...
Page 414 1 0 0 A A A A A A A A A A A A a Instruction Fields displacement AAAAAAAAAA0 10-bit signed PC relative displacement (<label) displacement 20-bit signed PC relative displacement aaaaaAAAAAAAAAAAAAAA0 (>label) A-100 SC140 DSP Core Reference Manual...
Page 415: Brad
#$1234,d0.l ;loads d0 brad lbl3 ; disassembled code - brad >*+a; p:lbl3 add d0,d1,d7 ; executes, d7 = $1234, pc then branches to $e, address of lbl3 lbl3 add d0,d7,d7 ; executes, d7 = $2468 SC140 DSP Core Reference Manual A-101...
Page 416 Note 1: The branch uses 4 cycles minus the execution time used by execution set in the delay slot. The cycle count for this instruction cannot be less than 1 cycle. Instruction Fields displacement AAAAAAAAAA0 10-bit signed PC relative displacement (<label) displacement 20-bit signed PC relative displacement aaaaaAAAAAAAAAAAAAAA (>label) A-102 SC140 DSP Core Reference Manual...
Page 417: Break
Note: The assembler has calculated the displacement $C to increment the program counter from its value at the BREAK ($0000 0014) to its value at _label ($0000 0020). LF3 is cleared by the break. SC140 DSP Core Reference Manual A-103...
Page 418 1 0 0 A A A A A A A A A A A A a Instruction Fields displacement aAAAAAAAAAAAAAAA0 16-bit signed PC relative displacement. The encoding is the displacement with bit 0 stripped and replaced by the sign bit. A-104 SC140 DSP Core Reference Manual...
Page 419: Bsr
Status and Conditions Changed by Instruction None. Example bsr _label Register/Memory Address Before After $00E0 0000 $0000 0014 _label (displacement) $0000 0002 $0000 0016 $0000 0006 ($30) $00E0 0000 ($34) SC140 DSP Core Reference Manual A-105...
Page 420 1 0 0 A A A A A A A A A A A A a Instruction Fields displacement AAAAAAAA0 8-bit signed PC relative displacement (<label) displacement 20-bit signed PC relative displacement aaaaaAAAAAAAAAAAAAA (>label) A-106 SC140 DSP Core Reference Manual...
Page 421: Bsrd
; initializes sp, sp is esp in this example tfra r1,osp ; initializes osp, osp is nsp bsrd lbl3 ; branch to lbl3 move.w #$1234,r0 ; execute before the branch lbl3 add d0,d1,d2 SC140 DSP Core Reference Manual A-107...
Page 422 BSRD and the execution time of the delay slot set is ≥ 4. One cycle is used by the core to push the return address onto the stack. Instruction Fields displacement 8-bit signed PC relative displacement AAAAAAAA0 (<label) displacement aaaaaAAAAAAAAAAAAAA 20-bit signed PC relative displacement (>label) A-108 SC140 DSP Core Reference Manual...
Page 423 - - - - Skipped over. - - - - Skipped over. - - - - Execution continues here at lbl, d4=$16. lbl move.w #$16,d4 Register/Memory Address Before BT After $00E4 0002 $0035 $0029 SC140 DSP Core Reference Manual A-109...
Page 424 Note 1: If the branch is not taken, it uses 1 cycle. If the branch is taken, it uses 4 cycles. Instruction Fields displacement 8-bit signed PC relative displacement AAAAAAAA0 (<label) displacement aaaaaAAAAAAAAAAAAAA 20-bit signed PC relative displacement (>label) A-110 SC140 DSP Core Reference Manual...
Page 425: Btd
#$47,d2 Skipped over. - - - - Skipped over. - - - - - - - - Skipped over. lbl move.w #$1A,d4 Execution continues here at lbl. Register/Memory Address Before BTD After $00E0 0002 SC140 DSP Core Reference Manual A-111...
Page 426 The cycle count for this instruction cannot be less than 1 cycle. Instruction Fields displacement AAAAAAAA0 8-bit signed PC relative displacement (<label) displacement 20-bit signed PC relative displacement aaaaaAAAAAAAAAAAAAA (>label) A-112 SC140 DSP Core Reference Manual...
Page 427 Clear the Ln bit in the destination data register. Example clb d3,d7 Register/Memory Address Before After $00000 F7434 L7:D7 $0:$FF FFFF FFF5 The number of consecutive zeros is 20, 9 - 20 = -11 ($FFF5) SC140 DSP Core Reference Manual A-113...
Page 428 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-114 SC140 DSP Core Reference Manual...
Page 429 1 0 1 1 F F F 0 0 CLR Dn (Da even) 1 0 0 0 F F F 1 1 0 0 1 CLR Dn (Da odd) Note: ** indicates serial grouping encoding. SC140 DSP Core Reference Manual A-115...
Page 430 Source Data Register 10000 11100 10100 11110 Note: This instruction can specify D8-D15 as operands by using a prefix. Source Data Register Note: If registers D8–D15 are accessed instead of D0–D7, a prefix is used. A-116 SC140 DSP Core Reference Manual...
Page 431 1 1 0 0 F F F 1 1 0 0 CMPEQ Da,Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-117...
Page 432 CMPEQ Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-118 SC140 DSP Core Reference Manual...
Page 433 Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] Sets T bit if equal, otherwise cleared. Example cmpeq.w #$5,d3 Register/Memory Address Before After immediate $0000 0005 $00 0000 0005 $00E4 0000 $00E4 0002 SC140 DSP Core Reference Manual A-119...
Page 434 CMPEQ.W #s16,Dn 1 0 0 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. iiiii 5-bit unsigned immediate data #s16 iiiiiiiiiiiiiiii 16-bit signed immediate data A-120 SC140 DSP Core Reference Manual...
Page 435 Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] Sets T bit if equal, otherwise cleared. Example cmpeqa r1,r2 Register/Memory Address Before After $0000 0005 $0000 0005 $00E4 0000 $00E4 0002 SC140 DSP Core Reference Manual A-121...
Page 436 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-122 SC140 DSP Core Reference Manual...
Page 437 1 1 0 0 F F F 1 1 1 0 CMPGT Da,Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-123...
Page 438 CMPGT Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-124 SC140 DSP Core Reference Manual...
Page 439 Register Address Bit Name Description SR[1] Sets T bit if Dn > an immediate, otherwise cleared. Example cmpgt.w #$8002,d2 Register/Memory Address Before After immediate $FF FFFF 8002 $FF FFFF 8004 $00E4 0000 $00E4 0002 SC140 DSP Core Reference Manual A-125...
Page 440 CMPGT.W #s16,Dn 1 0 0 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. iiiii 5-bit unsigned immediate data #s16 iiiiiiiiiiiiiiii 16-bit signed immediate data A-126 SC140 DSP Core Reference Manual...
Page 441 Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] Sets the T bit if Rx > rx, otherwise cleared. Example cmpgta r2,r3 Register/Memory Address Before After $0000 35FA $0000 34EA $00E4 0002 $00E4 0000 SC140 DSP Core Reference Manual A-127...
Page 442 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-128 SC140 DSP Core Reference Manual...
Page 443 1 1 0 0 F F F 1 1 1 1 CMPHI Da,Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-129...
Page 444 CMPHI Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-130 SC140 DSP Core Reference Manual...
Page 445 Status and Conditions Changed By Instruction Register Address Bit Name Description SR[1] Sets the T bit if unsigned Rx > rx, otherwise cleared. Example cmphia r0,r1 Register/Memory Address Before After $FFFF 8002 $FFFF FFFF $00E4 0000 $00E4 0002 SC140 DSP Core Reference Manual A-131...
Page 446 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-132 SC140 DSP Core Reference Manual...
Page 447 $40E4 0000 $00E4 0000 $0000 0014 $0000 0020 Loop count 3 (LC3) is 1, so loop count is decremented to 0, loop flag 3 (SR26) is cleared, and program continues at _label, address $0000 0020. SC140 DSP Core Reference Manual A-133...
Page 448 Note 1: If LC > 1, CONT uses 3 cycles. If LC ≤ 1, CONT uses 4 cycles. Instruction Fields displacement aAAAAAAAAAAAAAAA0 16-bit signed PC relative displacement. The encoding is the displacement with bit 0 stripped and replaced by the sign bit. A-134 SC140 DSP Core Reference Manual...
Page 449 ; DALU instruction at start address add d5,d6,d7 contd lbl3 ; PC returns to strt0 until LC = 1 ; executes in the delay slot each time, PC jumps to lbl3 when LC = 1 inc d1 SC140 DSP Core Reference Manual A-135...
Page 450 The cycle count for this instruction cannot be less than 1 cycle. Instruction Fields displacement aAAAAAAAAAAAAAAA0 16-bit signed PC relative displacement. The encoding is the displacement with bit 0 stripped and replaced by the sign bit. A-136 SC140 DSP Core Reference Manual...
Page 451 Status and Conditions Changed by Instruction None. Example debug Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0 0 DEBUG SC140 DSP Core Reference Manual A-137...
Page 452 None. Status and Conditions Changed by Instruction None. Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 DEBUGEV A-138 SC140 DSP Core Reference Manual...
Page 453 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-139...
Page 454 DECA 5-bit unsigned immediate data = 1, set by the assembler iiiii A-140 SC140 DSP Core Reference Manual...
Page 455 $00E4 0002 $0000 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 F F F 1 1 0 1 1 0 1 DECEQ Dn Note: ** indicates serial grouping encoding. SC140 DSP Core Reference Manual A-141...
Page 456 DECEQ Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-142 SC140 DSP Core Reference Manual...
Page 457 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SP cannot be used as an operand for this instruction. SC140 DSP Core Reference Manual A-143...
Page 458 ;$00E4 0001 T-bit cleared, carry bit set $FF FFFF FFFF Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 F F F 1 1 0 1 1 0 0 DECGE Dn Note: ** indicates serial grouping encoding. A-144 SC140 DSP Core Reference Manual...
Page 459 DECGE Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-145...
Page 460 Set if result ≥ 0, cleared otherwise. SR[1] Example 1 decgea r4 Register/Memory Address Before After $0010 E438 $0010 E437 $00E4 0000 $00E4 0002 Example 2 decgea r4 Register/Memory Address Before After $8000 0000 $7FFF FFFF $00E4 0002 $00E4 0000 A-146 SC140 DSP Core Reference Manual...
Page 461 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SP cannot be used by this instruction. SC140 DSP Core Reference Manual A-147...
Page 462 Status and Conditions Changed by Instruction Register Address Bit Name Description SR[19] Set disable interrupt bit. Example 1 Register/Memory Address Before After $0000 0000 $0008 0000 $0000 0000 $0000 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode A-148 SC140 DSP Core Reference Manual...
Page 463 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 1 SC140 DSP Core Reference Manual A-149...
Page 464 2. Shift the partial remainder and the quotient: Dn is shifted one bit to the left. The carry bit C is moved into bit 0 of Dn. The carry bit represents the quotient bit generated by the previous DIV iteration. A-150 SC140 DSP Core Reference Manual...
Page 465 Calculates and updates the Ln bit in the destination register. Example div d2,d1 Register/Memory Address Before After $00 2311 5A3B L1:D1 $0:$00 6666 0A57 $0:$00 A9BB 14AE $00E4 0000 $00E4 0001 $0000 0000 SC140 DSP Core Reference Manual A-151...
Page 466 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-152 SC140 DSP Core Reference Manual...
Page 467 Before After $00 0002 0000 $00 0003 0000 L5:D5 $0:$00 0050 0000 $0:$00 0000 005C $0000 0000 $00 0002 0000 x $00 0003 0000 $00 0000 000C + $00 0000 0050 $00 0000 005C SC140 DSP Core Reference Manual A-153...
Page 468 Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-154 SC140 DSP Core Reference Manual...
Page 469 $0:$FF FFE5 E345 $0000 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 1 1 F F F 1 1 1 0 0 e e DMACSU Dc,Dd,Dn Note: ** indicates serial grouping encoding. SC140 DSP Core Reference Manual A-155...
Page 470 Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-156 SC140 DSP Core Reference Manual...
Page 471 Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[30:27] LF[3:0] Sets active loopflag. Example doen2 d0 Register/Memory Address Before After $00 0000 000F $0000 000F $00E4 0000 $20E4 0000 SC140 DSP Core Reference Manual A-157...
Page 472 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. iiiiii 6-bit unsigned immediate data #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii A-158 SC140 DSP Core Reference Manual...
Page 473 Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[30:27] LF[3:0] Sets active loopflag. SR[31] Sets short loopflag. Example doensh2 d0 Register/Memory Address Before After $00 0000 000F $0000 000F SC140 DSP Core Reference Manual A-159...
Page 474 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. iiiiii 6-bit unsigned immediate data #u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data A-160 SC140 DSP Core Reference Manual...
Page 475 SA. In case of a conflict between the two, SA is defined by DOSETUPn. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction None. Example dosetup1 _label Register/Memory Address Before After (displacement) $101E $0000 0002 $0000 1020 SC140 DSP Core Reference Manual A-161...
Page 476 Instruction Fields Loop Identifier Loop 0 Loop 1 Loop 2 Loop 3 displacement aAAAAAAAAAAAAAAA0 16-bit signed PC relative displacement. The encoding is the displacement with bit 0 stripped and replaced by the sign bit. A-162 SC140 DSP Core Reference Manual...
Page 477 Clears disable interrupt bit. Example Register/Memory Address Before After $EC0000 $E40000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 SC140 DSP Core Reference Manual A-163...
Page 478 A-164 SC140 DSP Core Reference Manual...
Page 479 Register Address Bit Name Description Clears the Ln bit in the destination register. Example eor d4,d5 Register/Memory Address Before After $FF FFFF FFFB L5:D5 $0:$00 0000 0003 $0:$FF FFFF FFF8 1011 ⊕3 0011 1000 SC140 DSP Core Reference Manual A-165...
Page 480 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-166 SC140 DSP Core Reference Manual...
Page 481 Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination register. Example eor #$5,d5.l Register/Memory Address Before After immediate $0005 $0000 0003 $0000 0006 0101 ⊕3 0011 0110 SC140 DSP Core Reference Manual A-167...
Page 482 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. #u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data A-168 SC140 DSP Core Reference Manual...
Page 483 Register Address Bit Name Description SR[18] Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None. SC140 DSP Core Reference Manual A-169...
Page 484 This instruction can specify R8-R15 as operands by using a high register prefix. 16-bit unsigned absolute address AAAAAAAAAAAAAAAA #u16 16-bit unsigned immediate data iiiiiiiiiiiiiiii AAAAA0 5-bit unsigned SP address offset AAAAAAAAAAAAAAAA 16-bit signed SP address offset A-170 SC140 DSP Core Reference Manual...
Page 485 Register Address Bit Name Description Clears the Ln bit in the destination register. Example extract #$c,#$e,d2,d4 Register/Memory Address Before After immediate (width) immediate (offset) $FF 8665 4321 L4:D4 $0:$00 0000 0000 $0:$FF FFFF F995 SC140 DSP Core Reference Manual A-171...
Page 486 This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. #u16 iiiiii Unsigned 6-bit integer #U16 IIIIII Unsigned 6-bit integer A-172 SC140 DSP Core Reference Manual...
Page 487 Register Address Bit Name Description Clears the Ln bit in the destination register. Example extractu #$c,#$e,d2,d4 Register/Memory Address Before After immediate (width) immediate (offset) $FF 8665 4321 L4:D4 $0:$00 0000 0000 $0:$00 0000 0995 SC140 DSP Core Reference Manual A-173...
Page 488 This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. #u16 iiiiii unsigned 6-bit integer #U16 unsigned 6-bit integer IIIIII A-174 SC140 DSP Core Reference Manual...
Page 489 1 0 F F F IADDNC.W #s16,Dn 1 0 0 Instruction Fields Single Source/Destination Data Register Note: If registers D8–D15 are accessed instead of D0–D7, a prefix is used. #s16 iiiiiiiiiiiiiiii 16-bit signed immediate data SC140 DSP Core Reference Manual A-175...
Page 490 2. The “IFA group” is the same as not using IFc. That is, unconditional execution of the VLES. 3. The detailed use of IFc is defined by Section 7.2, “VLES Grouping Semantics,” programming rule G.P.7 in Section 7.5.3, “Prefix Grouping Rules.” A-176 SC140 DSP Core Reference Manual...
Page 491 For example, a full execution set might be D0, D1, D2, D3, A0, 000—Unconditionally executed 001—If true (D0,D2,A0), if false (D1,D3,A1) 010—If true, all the set 011—If false, all the set 100—Reserved 101—Reserved 110—If true (D0,D2,A0), always (D1,D3,A1) 111—If false (D0,D2,A0), always (D1,D3,A1) SC140 DSP Core Reference Manual A-177...
Page 492: C (Carry Bit)
PC_EXCP register in the EOnCE (see the EOnCE section for a description of this register). The AGU sets the EXP bit in SR to switch the active stack pointer to the exception stack pointer. . A-178 SC140 DSP Core Reference Manual...
Page 493 1 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0 ILLEGAL Note 1: Cycle count is dependant on the machine state. Typically, five cycles is the service time for an illegal request. SC140 DSP Core Reference Manual A-179...
Page 494 Set if the result cannot be represented in 40 bits. Example 1 imac d4,d5,d6 Register/Memory Address Before After $FF FFFF FFFB $00 0000 0003 L6:D6 $0:$00 0000 0008 $0:$FF FFFF FFF9 $0000 0000 $0000 0000 A-180 SC140 DSP Core Reference Manual...
Page 495 Opcode IMAC ±Da,Db,Dn 1 0 1 0 F F F k IMAC ±Da,Da,Dn 1 0 1 0 F F F 1 1 0 Note: ** indicates serial grouping encoding. Instruction Fields Accumulation Notation subtract SC140 DSP Core Reference Manual A-181...
Page 496 Data Register Pairs D1,D1 D3,D3 D5,D5 D7,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-182 SC140 DSP Core Reference Manual...
Page 497 Set if the result cannot be represented in 40 bits. Example imaclhuu d3,d4,d0 Register/Memory Address Before After $00 0000 0002 $FF FFC0 0000 L0:D0 $0:$00 0000 0001 $0:$00 0001 FF81 $0000 0000 –65,472$FFC0 $0002 –130,944$FF80 $0001 -130,943$FF81 SC140 DSP Core Reference Manual A-183...
Page 498 This instruction can specify D8-D15 as operands by using a prefix. Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-184 SC140 DSP Core Reference Manual...
Page 499 EMR[2] DOVF Set if the result cannot be represented in 40 bits. Example imacus d3,d4,d0 Register/Memory Address Before After $00 7CE8 0002 $FF FFC0 F0D0 L0:D0 $0:$00 0000 0000 $0:$FF FFFF FF80 $0000 0000 SC140 DSP Core Reference Manual A-185...
Page 500 This instruction can specify D8-D15 as operands by using a prefix. Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-186 SC140 DSP Core Reference Manual...
Page 501 Words Cycles Type Opcode 1 0 1 0 F F F 1 1 1 0 1 IMPY Da,Da,Dn 1 0 1 0 F F F 0 1 IMPY Da,Db,Dn Note: ** indicates serial grouping encoding. SC140 DSP Core Reference Manual A-187...
Page 502 The JJJJJ encoding does not include the pairs: D1–D1, D3–D3, D5–D5, D7–D7. These are covered in the jj encoding. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-188 SC140 DSP Core Reference Manual...
Page 503 Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination register. Example impy.w #$fffe,d3 Register/Memory Address Before After immediate $FFFE $00 7FFF FFF8 $00 0000 0010 SC140 DSP Core Reference Manual A-189...
Page 504 1 0 F F F IMPY.W #s16,Dn 1 0 0 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. #s16 16-bit signed immediate data iiiiiiiiiiiiiiii A-190 SC140 DSP Core Reference Manual...
Page 505 Register/Memory Address Before After $00 0002 FFFF $FF FFFF FFFE L0:D0 $0:$00 FFFE 0001 Example 2 impyhluu d4,d3,d0 Register/Memory Address Before After $00 0000 FFFF $FF FFFF FFFE L0:D0 $0:$00 FFFE 0001 SC140 DSP Core Reference Manual A-191...
Page 506 This instruction can specify D8-D15 as operands by using a prefix. Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-192 SC140 DSP Core Reference Manual...
Page 507 Status and Conditions Changed by Instruction Register Bit Name Description Address Clears the Ln bit in the destination register. Example impysu d3,d5,d1 Register/Memory Address Before After $00 0000 0122 $FF FFFF FFFF L1:D1 $0:$FF FFFF FEDE SC140 DSP Core Reference Manual A-193...
Page 508 This instruction can specify D8-D15 as operands by using a prefix. Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-194 SC140 DSP Core Reference Manual...
Page 509 0 0 F F F IMPYUU Da,Db,Dn 1 0 0 0 0 0 0 0 0 0 0 0 0 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-195...
Page 510 IMPYUU Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-196 SC140 DSP Core Reference Manual...
Page 511 (SR [SM] = 1), clears the Ln bit in the destination register. Example 1 inc d0 Register/Memory Address Before After L0:D0 $0:$FF FFFF FFFF $0:$00 0000 0000 $00E4 0000 $00E4 0001 $0000 0000 SC140 DSP Core Reference Manual A-197...
Page 512 1 1 1 0 F F F 1 0 0 0 0 0 1 INC Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-198 SC140 DSP Core Reference Manual...
Page 513 (SR [SM] = 1), clears the Ln bit in the destination register. Example inc.f d15 Register/Memory Address Before After L0:D15 $0:$FF FFFF FFFF $0:$00 0000 FFFF $00E4 0000 $00E4 0001 $0000 0000 SC140 DSP Core Reference Manual A-199...
Page 514 1 0 0 1 F F F 1 1 0 0 1 1 1 INC.F Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-200 SC140 DSP Core Reference Manual...
Page 515 Status and Conditions Changed by Instruction None. Example 1 inca r0 Register/Memory Address Before After MCTL $0000 0000 $074F 312A $074F 312B Example 2 inca r0 Register/Memory Address Before After MCTL $0000 0000 $FFFF FFFF $0000 0000 SC140 DSP Core Reference Manual A-201...
Page 516 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. iiiii 5-bit unsigned immediate data = 1, set by the assembler A-202 SC140 DSP Core Reference Manual...
Page 517 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 SC140 DSP Core Reference Manual...
Page 518 This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. iiiiii unsigned 6-bit integer IIIIII unsigned 6-bit integer A-204 SC140 DSP Core Reference Manual...
Page 519 #$47,d2 Skipped over. - - - - Skipped over. - - - - Skipped over. - - - - Execution continues here at lbl. lbl move.w #$1A,d4 Register/Memory Address Before After $00E0 0000 SC140 DSP Core Reference Manual A-205...
Page 520 Note 1: If the branch is not taken, it uses 1 cycle. If the branch is taken, it uses 4 cycles. Instruction Fields Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. label 32-bit absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA Note: Label must be word-aligned, LSBit = 0. A-206 SC140 DSP Core Reference Manual...
Page 521 Increment d1 to $2A. inc d1 Skipped over. move.w #$47,d2 Skipped over. - - - - Skipped over. - - - - Skipped over. - - - - Execution continues here at lbl. adr move.w #$1A,d4 SC140 DSP Core Reference Manual A-207...
Page 522 The cycle count for this instruction cannot be less than 1 cycle. Instruction Fields Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. label 32-bit absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA Note: Label must be word-aligned, LSBit = 0. A-208 SC140 DSP Core Reference Manual...
Page 523 Jumps to a memory address specified by an address register (Rn). The value in Rn must be word-aligned. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction None. Example jmp _label Register/Memory Address Before After _label (absolute) $0000 000A $0000 0002 $0000 000A SC140 DSP Core Reference Manual A-209...
Page 524 JMP Rn Instruction Fields Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. label 32-bit absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA Note: Label must be word-aligned, LSBit = 0. A-210 SC140 DSP Core Reference Manual...
Page 525 Increment executed in the delay slot, d1 = $2A. inc d1 Skipped over. move.w #$20,d3 Skipped over. - - - - Skipped over. - - - - Skipped over. - - - - Execution continues here at lbl. lbl move.w #$16,d4 SC140 DSP Core Reference Manual A-211...
Page 526 1 cycle. Instruction Fields label aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAAA 32-bit absolute long address Note: Label must be word-aligned, LSBit = 0. Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-212 SC140 DSP Core Reference Manual...
Page 527 Determines which stack pointer is used. Status and Conditions Changed by Instruction None. Example jsr r6 Register/Memory Address Before After $0000 0012 $0000 0004 $0000 0012 $0000 0100 $00000108 $00E0 0000 ($00000100) $0000 000A ($00000104) $00E0 0000 SC140 DSP Core Reference Manual A-213...
Page 528 Note 1: The cycle time is 4 if the largest execution time of the other instructions grouped with JSR is ≥ 3. Instruction Fields label absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA Note: Label must be word-aligned, LSBit = 0. Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-214 SC140 DSP Core Reference Manual...
Page 529 Increment executed in the delay slot, d1=$2A. inc d1 Skipped over. - - - - Skipped over. - - - - Skipped over. - - - - Execution continues here at subroutine. subroutine move.w #$16,d4 SC140 DSP Core Reference Manual A-215...
Page 530 The cycle count for this instruction cannot be less than one cycle. Instruction Fields label absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA Note: Label must be word-aligned, LSBit = 0. Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-216 SC140 DSP Core Reference Manual...
Page 531 Status and Conditions that Affect Instruction Register Address Bit Name Description SR[1] True bit Status and Conditions Changed by Instruction None. Example jt r0 Register/Memory Address Before After $0000 0010 $00E4 0002 $0000 0006 $0000 0010 SC140 DSP Core Reference Manual A-217...
Page 532 Note 1: If not taken, the jump uses 1 cycle. If taken, the jump uses 4 cycles. Instruction Fields label absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA Note: Label must be word-aligned, LSBit = 0. Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-218 SC140 DSP Core Reference Manual...
Page 533 Increment executed in the delay slot. inc d1 Skipped over. - - - - Skipped over. - - - - Skipped over. - - - - Execution continues here at ADRESS. ADRESS move.w #$16,d4 SC140 DSP Core Reference Manual A-219...
Page 534 The cycle count for this instruction cannot be less than 1 cycle. Instruction Fields label absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA Note: Label must be word-aligned, LSBit = 0. Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-220 SC140 DSP Core Reference Manual...
Page 535 The LPMARK bits are encoded in the prefix words, and are not independent instructions. They are generated automatically by the assembler at the correct positions based on the LOOPSTART and LOOPEND assembly directives inserted by the programmer. The assembler does not allow the programmer to use LPMARKx. SC140 DSP Core Reference Manual A-221...
Page 536: Combinations Of Lpmarkx Use
The active inner loop is terminated and the LPMARKB is executed. Status and Conditions that Affect LPMARK Execution The loop flag (LFn), short loop flag (SLFn), and loop counters (LCn) affect the response as described in the description above. A-222 SC140 DSP Core Reference Manual...
Page 537 1 0 1 b B e E T b B e E b B e E Note: If LPMARKA is present, j = 1. If LPMARKB is present, p = 1. The other bits shown in the encoding table are independent of LPMARKx. SC140 DSP Core Reference Manual A-223...
Page 538 Dn is stored in the C bit for a right shift. Clears the Ln bit in the destination register. Example 1 lsll d4,d2 Register/Memory Address Before After $00 0000 0002 $00E4 0000 $00E4 0001 L2:D2 $0:$FF 8765 4321 $0:$FE 1D95 0C84 A-224 SC140 DSP Core Reference Manual...
Page 539 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-225...
Page 540 1 0 0 1 F F F 1 1 0 1 1 1 0 LSR Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-226 SC140 DSP Core Reference Manual...
Page 541 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-227...
Page 542 5-bit integer immediate. Bit (N – 1) is stored in the C bit. Bits[ 39:N] are copied to bits [(39 – N):0]. Bits [39:(40 – N)] are cleared. Status and Conditions that Affect Instruction None. A-228 SC140 DSP Core Reference Manual...
Page 543 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 SC140 DSP Core Reference Manual...
Page 544 Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. iiiii 5-bit unsigned immediate data A-230 SC140 DSP Core Reference Manual...
Page 545 SR[0] Dn[15] is copied into the C bit. Clears the Ln bit in the destination register. Example lsrw d4,d2 Register/Memory Address Before After $FF 8765 4321 L2:D2 $0:$00 00FF 8765 $00E4 0000 $00E4 0000 SC140 DSP Core Reference Manual A-231...
Page 546 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-232 SC140 DSP Core Reference Manual...
Page 547 Set if the result cannot be represented in 40 bits, or if the result saturates to 32 bits in arithmetic saturation mode. Example 1 mac d4,d5,d6 Register/Memory Address Before After $00E0 0000 $00 1000 0000 SC140 DSP Core Reference Manual A-233...
Page 548 1 0 0 MAC ±Da,Db,Dn 1 0 0 0 F F F k MAC ±Da,Da,Dn 1 0 1 0 F F F 1 1 Note: ** indicates serial grouping encoding. Instruction Fields Accumulation Notation subtract A-234 SC140 DSP Core Reference Manual...
Page 549 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. #s16 iiiiiiiiiiiiiiii 16-bit signed immediate data SC140 DSP Core Reference Manual A-235...
Page 550 Set if the result cannot be represented in 40 bits, or if the result saturates to 32 bits in arithmetic saturation mode. Example macr d4,d5,d6 Register/Memory Address Before After $00E0 0000 $00 0080 0000 $00 0080 0000 L6:D6 $0:$00 0007 0000 $0:$00 0008 0000 A-236 SC140 DSP Core Reference Manual...
Page 551 Register pair order can be inverted for clarity because the order of operation is not important for multiply operations. The JJJJJ encoding does not include the pairs: D1–D1, D3–D3, D5–D5, and D7–D7. These are covered in the jj encoding. SC140 DSP Core Reference Manual A-237...
Page 552 Data Register Pairs D1,D1 D3,D3 D5,D5 D7,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-238 SC140 DSP Core Reference Manual...
Page 553 EMR[2] DOVF Set if the result cannot be represented in 40 bits. Example macsu d0,d1,d4 Register/Memory Address Before After $FF C000 0000 $00 0000 0001 L4:D4 $0:$00 0000 0000 $0:$FF FFFF 8000 $0000 0000 SC140 DSP Core Reference Manual A-239...
Page 554 Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-240 SC140 DSP Core Reference Manual...
Page 555 $FF C000 0000 L4:D4 $0:$00 3FFF 8000 $0:$00 3fff 0000 $0000 0000 –15 $0001 x 1.100 $C000 1.111 1111 1111 1111 1000$FFFF 8000 0.011 1111 1111 1111 1000$3FFF 8000 0.011 1111 1111 1111 0000$3FFF SC140 DSP Core Reference Manual A-241...
Page 556 Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-242 SC140 DSP Core Reference Manual...
Page 557 1.111 1111 1111 1111$FFFF 1 1.111 1111 1111 1100 0000 0000 0000 0001$01 FFFC 0001 + 0.111 1111 1111 1111 1111 1111 1111 1111$00 7FFF FFFF 10 0.111 1111 1111 1100 0000 0000 0000 0001$02 7FFC 0001 SC140 DSP Core Reference Manual A-243...
Page 558 Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-244 SC140 DSP Core Reference Manual...
Page 559 Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction None. Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 1 1 1 0 0 1 1 1 0 0 MARK SC140 DSP Core Reference Manual A-245...
Page 560 1 0 1 1 G G 0 1 1 1 1 1 0 0 MAX Dg,Dh Note: ** indicates serial grouping encoding. Instruction Fields Dg,Dh Data Register Pairs D0,D4 D1,D5 D2,D6 D3,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. A-246 SC140 DSP Core Reference Manual...
Page 561 $0:$00 0FE4 0023 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 1 1 G G 0 1 1 1 1 1 1 1 MAX2 Dg,Dh Note: ** indicates serial grouping encoding. SC140 DSP Core Reference Manual A-247...
Page 562 MAX2 Instruction Fields Dg,Dh Data Register Pairs D0,D4 D1,D5 D2,D6 D3,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. A-248 SC140 DSP Core Reference Manual...
Page 563 (n=1, 3) if the HP of Da is not greater than the HP of Db. The high bank of registers can also be used: D12 and D8 substituted for Da, and D10 and D14 substituted for Db. The encoding for the substitution is done with a prefix. Status and Conditions that Affect Instruction None. SC140 DSP Core Reference Manual A-249...
Page 564 1 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 MAX2VIT D0,D6 Note: This instruction can specify D12, D10, D8, and D14 instead of D4, D2, D0, and D6 by using a prefix. A-250 SC140 DSP Core Reference Manual...
Page 565 $FFDD = –35, $0022 = +34 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 1 1 G G 0 1 1 1 1 1 1 0 MAXM Dg,Dh Note: ** indicates serial grouping encoding. SC140 DSP Core Reference Manual A-251...
Page 566 MAXM Instruction Fields Dg,Dh Data Register Pairs D0,D4 D1,D5 D2,D6 D3,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. A-252 SC140 DSP Core Reference Manual...
Page 567 1 0 1 1 G G 0 1 1 1 1 1 0 1 MIN Dg,Dh Note: ** indicates serial grouping encoding. Instruction Fields Dg,Dh Data Register Pairs D0,D4 D1,D5 D2,D6 D3,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-253...
Page 568 Set if big endian mode, cleared if little endian mode. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example move.2f (r7),d2:d3 Register/Memory Address Before After MCTL $0000 0000 $0000 0050 A-254 SC140 DSP Core Reference Manual...
Page 569 Effective Address Notation (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-255...
Page 570 Set if big endian mode, cleared if little endian mode. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example move.2l d0:d1,(r0) Register/Memory Address Before After MCTL $0000 0000 A-256 SC140 DSP Core Reference Manual...
Page 571 Effective Address Notation (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-257...
Page 572 Set if big endian mode, cleared if little endian mode. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example move.2w d0:d1,(r0) Register/Memory Address Before After MCTL $0000 0000 A-258 SC140 DSP Core Reference Manual...
Page 573 Effective Address Notation (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-259...
Page 574 MCTL. EMR[16] Set if big endian mode, cleared if little endian mode. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example A-260 SC140 DSP Core Reference Manual...
Page 575 Effective Address Notation (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-261...
Page 576 MCTL. EMR[16] Set if big endian mode, cleared if little endian mode. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example A-262 SC140 DSP Core Reference Manual...
Page 577 Effective Address Notation (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-263...
Page 578 15-bit offset. MOVE.B (ea),DR Reads a byte from memory, sign-extending it into a register. The effective memory address is obtained from an address register with an optional offset or post-increment. A-264 SC140 DSP Core Reference Manual...
Page 579 Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example move.b d3,(r7+$3) Register/Memory Address Before After MCTL $0000 0000 $FF FFFF FFF8 $0000 0050 $00000053 SC140 DSP Core Reference Manual A-265...
Page 580 Data/Address Register 0000 0100 1000 1100 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. A-266 SC140 DSP Core Reference Manual...
Page 581 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. Effective Address Notation )– +N0) AAAAAAAAAAAAAAAA 16-bit unsigned absolute address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32-bit absolute long address Signed 15-bit offset sssssssssssssss SC140 DSP Core Reference Manual A-267...
Page 582 MOVE.F (Rn+s15),Db Reads a fractional word from memory into a data register. The effective memory address is obtained from an address register with a signed 15-bit offset. A-268 SC140 DSP Core Reference Manual...
Page 583 Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example move.f ($54),d10 Register/Memory Address Before After $00000054 $6000 L10:D10 $0:$00 6000 0000 SC140 DSP Core Reference Manual A-269...
Page 584 When the form (Rn + N0) is used in EA or ea, the cycle count is increased by 1. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Effective Address Notation (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 A-270 SC140 DSP Core Reference Manual...
Page 585 Note: This instruction can specify R8-R15 as operands by using a high register prefix. #s16 16-bit signed immediate data iiiiiiiiiiiiiiii AAAAAAAAAAAAAAAA 16-bit unsigned absolute address 32-bit absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA sssssssssssssss Signed 15-bit offset SC140 DSP Core Reference Manual A-271...
Page 586 Register Address Bit Name Description Clears the Ln bit in the destination register. Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 0 0 1 1 D D D D 0 D 0 MOVE.L #s32,C4 A-272 SC140 DSP Core Reference Manual...
Page 587 Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. Single Source/Destination Data Register Note: If registers D8–D15 are accessed instead of D0–D7, a prefix is used. SC140 DSP Core Reference Manual A-273...
Page 588 MOVE.L Read/Write Notation write read #s32 32-bit signed immediate data (31)IIIIIIIIIIIIIIII(16) (15)iiiiiiiiiiiiiiii (0) #u32 32-bit unsigned immediate data (31)IIIIIIIIIIIIIIII(16) (15)iiiiiiiiiiiiiiii (0) A-274 SC140 DSP Core Reference Manual...
Page 589 MOVE.L (SP+s15),De.E Reads from a memory address pointed to by the stack pointer and a signed 15-bit offset into the extension and Ln bit of an even numbered data register. MOVE.L Da.E:Db.E,(SP+s15) SC140 DSP Core Reference Manual A-275...
Page 590 Register Address Bit Name Description Memory to register moves write the Ln bit in the destination register. Example move.l d0.e:d1.e,($1224) Register/Memory Address Before After L0:D0 $1:$FF FEDC BA98 L1:D1 $0:$00 1234 5678 $1224 $0000 01FF A-276 SC140 DSP Core Reference Manual...
Page 591 This instruction can specify D9, D11, D13, or D15 as operands instead of D1, D3, D5, or D7 by using a prefix. Da.E:Db.E ff Data Register Extension Pair D0.E:D1.E D2.E:D3.E D4.E:D5.E D6.E:D7.E Note: This instruction can specify D8-D15 as operands by using a prefix. AAAAAAAAAAAAAAA Signed 15-bit offset SC140 DSP Core Reference Manual A-277...
Page 592 MOVE.L aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32-bit absolute long address A-278 SC140 DSP Core Reference Manual...
Page 593 Absolute addresses, offsets, and address register values must be long word-aligned (the address must be a multiple of 4). The programmer should ensure that the effective address resides on a long word boundary. SIGN EXTENSION SC140 DSP Core Reference Manual A-279...
Page 594 MOVE.L (SP–u6),DR MOVE.L DR,(SP–u6) Moves a 32-bit long word between a data or address register and a memory address pointed to by the active stack pointer minus a 6-bit unsigned offset. A-280 SC140 DSP Core Reference Manual...
Page 595 1 0 0 A A A A A A A A A A A A A MOVE.L C4,(a16) 1 0 1 1 H H H H w 1 R R R s MOVE.L (Rn+u3),DR SC140 DSP Core Reference Manual A-281...
Page 596 0 0 0 w D D D D 1 1 1 0 D 0 MOVE.L (SP+s15),C4 1 0 0 MOVE.L C4,(SP+s15) Note 1: When the form (Rn + N0) is used in EA, the cycle count is increased by 1. A-282 SC140 DSP Core Reference Manual...
Page 597 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. Address Register Note: The Rr operand is limited to R0–R7. Read/Write Notation write read SC140 DSP Core Reference Manual A-283...
Page 598 MOVE.L AAAAAAAAAAAAAAAA 16-bit unsigned absolute address 32-bit absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA sssssssssssssss Signed 15-bit offset sss00 Unsigned 3-bit offset Unsigned 6-bit SP offset ssssss00 A-284 SC140 DSP Core Reference Manual...
Page 599 Writes an immediate signed 16-bit value to a memory address pointed to by an address register. MOVE.W #s16,(SP+sa16) Writes a 16-bit signed immediate value to a memory address pointed to by the active stack pointer (SP) plus a signed 16-bit offset. SC140 DSP Core Reference Manual A-285...
Page 600 Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination register. Example move.w #$0050,r7 Register/Memory Address Before After immediate $0000 0050 $0000 0050 A-286 SC140 DSP Core Reference Manual...
Page 601 10011 11011 00100 01100 10100 11100 00101 01101 10101 11101 00110 01110 10110 11110 00111 01111 10111 11111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-287...
Page 602 This instruction can specify R8-R15 as operands by using a high register prefix. 7-bit signed immediate data iiiiiii #s16 iiiiiiiiiiiiiiii 16-bit signed immediate data AAAAAAAAAAAAAAAA 16-bit unsigned absolute address sa16 Signed 16-bit offset AAAAAAAAAAAAAAAA Unsigned 5-bit SP offset AAAAA0 A-288 SC140 DSP Core Reference Manual...
Page 603 Moves a signed word between a data or address register (DR) and an absolute 32-bit address. MOVE.W (a16),C4 MOVE.W C4,(a16) Moves a signed word between a general register (C4) and an absolute 16-bit address. SC140 DSP Core Reference Manual A-289...
Page 604 (SP) minus a 6-bit unsigned offset. MOVE.W (SP+s15),C4 MOVE.W C4,(SP+s15) Moves a signed word between a general register (C4) and a memory address pointed to by the active stack pointer (SP) with a signed 15-bit offset. A-290 SC140 DSP Core Reference Manual...
Page 605 Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example move.w d1,(r7+4) Register/Memory Address Before After MCTL $0000 0000 $FF FFFF FFF1 $0000 000A $0000 000A $000E $FFF1 SC140 DSP Core Reference Manual A-291...
Page 606 0 0 0 w D D D D 0 1 1 0 D 0 MOVE.W (SP+s15),C4 1 0 0 MOVE.W C4,(SP+s15) 1 1 1 1 H H H H w 0 MOVE.W (SP–u6),DR MOVE.W DR,(SP–u6) A-292 SC140 DSP Core Reference Manual...
Page 607 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. Address Register Note: The Rr register file is limited to the lower bank R0–R7. SC140 DSP Core Reference Manual A-293...
Page 608 MOVE.W AAAAAAAAAAAAAAAA 16-bit unsigned absolute address 32-bit absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA sssssssssssssss Signed 15-bit offset sss0 Unsigned 3-bit offset Unsigned 6-bit SP offset ssssss0 A-294 SC140 DSP Core Reference Manual...
Page 609 Status and Conditions Changed by Instruction None. Example movet r0,r1 Register/Memory Address Before After $00E4 0002 $0000 0010 $0000 0010 Note: $00E4 0002 in the status register indicates that the true bit is set. SC140 DSP Core Reference Manual A-295...
Page 610 Instruction Fields Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-296 SC140 DSP Core Reference Manual...
Page 611 Scaling bit, set when the absolute value of either or both of the words moved (after scaling and limiting) is greater than or equal to 0.25 and less than 0.75. Example moves.2f d0:d1,(r0) Register/Memory Address Before After MCTL $0000 0000 SC140 DSP Core Reference Manual A-297...
Page 612 This instruction can specify D8-D15 as operands by using a prefix. Effective Address Notation (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-298 SC140 DSP Core Reference Manual...
Page 613 Scaling bit, set when the absolute value of any one of the words moved (after scaling and limiting) is greater than or equal to 0.25 and less than 0.75. Example moves.4f d0:d1:d2:d3,(r0) Register/Memory Address Before After $00E0 0000 SC140 DSP Core Reference Manual A-299...
Page 614 This instruction can specify D8-D15 as operands by using a prefix. Effective Address Notation (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-300 SC140 DSP Core Reference Manual...
Page 615 Writes the HP of a data register (Db) to a memory address pointed to by an address register (EA) with an optional offset or post-increment. MOVES.F Db,(SP+s15) Writes the HP of a data register (Db) to a memory address pointed to by the active stack pointer (SP) with a signed 15-bit offset. SC140 DSP Core Reference Manual A-301...
Page 616 $0000 0050 L0:D0 $1:$00 8000 0000 ($0050) $7FFF The Ln bit is set in d0, and the number in d0 is positive (bit 39 = 0), so the saturated value $7FFF is written to memory. A-302 SC140 DSP Core Reference Manual...
Page 617 (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. AAAAAAAAAAAAAAAA 16-bit unsigned absolute address 32-bit absolute long address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA SC140 DSP Core Reference Manual A-303...
Page 618 MOVES.4F sssssssssssssss Signed 15-bit offset A-304 SC140 DSP Core Reference Manual...
Page 619 0.25 and less than 0.75. Example moves.l d0,(r0) Register/Memory Address Before After $00E0 0000 $00E0 0000 $0000 0054 L0:D0 $1:$00 8000 0000 $00000054 $7FFF FFFF SC140 DSP Core Reference Manual A-305...
Page 620 This instruction can specify R8-R15 as operands by using a high register prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Effective Address Notation (Rn+N0) (Rn) (Rn)+N0 (Rn)+N2 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 A-306 SC140 DSP Core Reference Manual...
Page 621 (DR). MOVEU.B (SP+s15),DR Reads an unsigned byte from a memory address pointed to by the active stack pointer with a signed 15-bit offset into a data or address register (DR). SC140 DSP Core Reference Manual A-307...
Page 622 Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example moveu.b ($0053),d10 Register/Memory Address Before After ($0053) $0:$00 0000 00F8 A-308 SC140 DSP Core Reference Manual...
Page 623 This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. Effective Address Notation )– +N0) Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. AAAAAAAAAAAAAAAA 16-bit unsigned absolute address SC140 DSP Core Reference Manual A-309...
Page 624 MOVEU.B aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32-bit absolute long address Signed 15-bit offset sssssssssssssss A-310 SC140 DSP Core Reference Manual...
Page 625 Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination register. Example moveu.l #$fffffff8,d3 Register/Memory Address Before After Immediate $FFFF FFF8 $0:$00 FFFF FFFF8 SC140 DSP Core Reference Manual A-311...
Page 626 0 0 1 MOVEU.L #u32,Db 0 0 1 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. #u32 32-bit unsigned immediate data (31)IIIIIIIIIIIIIIII(16) (15)iiiiiiiiiiiiiiii (0) A-312 SC140 DSP Core Reference Manual...
Page 627 Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination register. Example moveu.w #$2345,d10.l Register/Memory Address Before After Immediate $2345 $0:$00 ABCD EFFF $0:$00 ABCD 2345 SC140 DSP Core Reference Manual A-313...
Page 628 0 0 0 1 1 0 0 1 MOVEU.W #u16,Db.L 1 0 1 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. #u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data A-314 SC140 DSP Core Reference Manual...
Page 629 Reads an unsigned word from a memory address pointed to by the active stack pointer (SP) with a signed 15-bit offset, places the data in the LP of a general register (C4), and zero-extends the upper bits. SC140 DSP Core Reference Manual A-315...
Page 630 Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example moveu.w (r7+2),d10 Register/Memory Address Before After MCTL $0000 0000 $0000 0050 (R7+2) $FFF8 $00 1010 0000 $00 0000 FFF8 A-316 SC140 DSP Core Reference Manual...
Page 631 Data/Address Register 0000 0100 1000 1100 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-317...
Page 632 (Rn)– (Rn)+ (Rn)+N1 (Rn)+N3 Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. AAAAAAAAAAAAAAAA 16-bit unsigned absolute address aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32-bit absolute long address sssssssssssssss Signed 15-bit offset A-318 SC140 DSP Core Reference Manual...
Page 633 Set if the result cannot be represented in 40 bits, or if the result saturates to 32 bits in saturation mode. Example 1 mpy d4,d5,d6 Register/Memory Address Before After $00E0 0000 $FF C000 0000 $00 2000 0000 L6:D6 $0:$FF F000 0000 $0000 0000 SC140 DSP Core Reference Manual A-319...
Page 634 Register pair order can be inverted for clarity because the order of operation is not important for multiply operations. The JJJJJ encoding does not include the pairs: D1–D1, D3–D3, D5–D5, and D7–D7. These are covered in the jj encoding. A-320 SC140 DSP Core Reference Manual...
Page 635 Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-321...
Page 636 Set if the result cannot be represented in 40 bits, or if the result saturates to 32 bits in saturation mode. Example mpyr d4,d5,d6 Register/Memory Address Before After $00E0 0000 $00 4001 0000 $00 4002 0000 A-322 SC140 DSP Core Reference Manual...
Page 637 Data Register Pairs D1,D1 D3,D3 D5,D5 D7,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-323...
Page 638 MPYR A-324 SC140 DSP Core Reference Manual...
Page 639 1 0 e e MPYSU Dc,Dd,Dn Note: ** indicates serial grouping encoding. Instruction Fields Dc,Dd Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-325...
Page 640 MPYSU Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-326 SC140 DSP Core Reference Manual...
Page 641 1.111 1111 1111 1111$FFFF (–2 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 0 F F F 1 1 1 0 1 e e MPYUS Dc,Dd,Dn Note: ** indicates serial grouping encoding. SC140 DSP Core Reference Manual A-327...
Page 642 Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-328 SC140 DSP Core Reference Manual...
Page 643 0.001 $1000 (2 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 1 1 F F F 1 1 0 1 1 e e MPYUU Dc,Dd,Dn Note: ** indicates serial grouping encoding. SC140 DSP Core Reference Manual A-329...
Page 644 Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-330 SC140 DSP Core Reference Manual...
Page 645 $0:$00 0765 1235 $0:$FF F89A EDCB $0000 0000 0000 0111 0110 0101 0001 0010 0011 0101 invert 1111 1000 1001 1010 1110 1101 1100 1010 add one 1111 1000 1001 1010 1110 1101 1100 1011 SC140 DSP Core Reference Manual A-331...
Page 646 1 0 0 1 F F F 1 1 0 0 1 0 0 NEG Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-332 SC140 DSP Core Reference Manual...
Page 647 None. Status and Conditions Changed by Instruction None. Example Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 SC140 DSP Core Reference Manual A-333...
Page 648 Opcode 1 1 0 1 1 0 F F F 0 0 0 0 NOT Da,Dn Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-334 SC140 DSP Core Reference Manual...
Page 649 Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-335...
Page 650 None. Status and Conditions Changed by Instruction Register Address Bit Name Description Clears the Ln bit in the destination registers. Example not D0.L Register/Memory Address Before After L0:D0 $1:$00 3FF2 FFFB $0:$00 3FF2 0004 A-336 SC140 DSP Core Reference Manual...
Page 651 Data/Address Register 0000 0100 1000 1100 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-337...
Page 652 Register Address Bit Name Description SR[18] Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None. A-338 SC140 DSP Core Reference Manual...
Page 653 Instruction Fields Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. AAAAAAAAAAAAAAAA 16-bit unsigned absolute address AAAAA0 Unsigned 5-bit address offset AAAAAAAAAAAAAAAA Signed 16-bit SP address offset SC140 DSP Core Reference Manual A-339...
Page 654 Opcode 1 1 0 1 1 1 F F F 0 0 1 1 OR Da,Dn Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-340 SC140 DSP Core Reference Manual...
Page 655 Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-341...
Page 656 Clears the Ln bit in the destination registers. Example or #$0f0a,d0.l Register/Memory Address Before After Immediate $0F0A $1:$00 ACBD F065 $0:$00 ACBD FF6F 0000 1111 0000 1010 or 1111 0000 0110 0101 1111 1111 0110 1111 A-342 SC140 DSP Core Reference Manual...
Page 657 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. #u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data SC140 DSP Core Reference Manual A-343...
Page 658 Register Address Bit Name Description SR[18] Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None. A-344 SC140 DSP Core Reference Manual...
Page 659 Instruction Fields Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. #u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data 16-bit unsigned absolute address AAAAAAAAAAAAAAAA Unsigned 5-bit SP address offset AAAAA0 SC140 DSP Core Reference Manual A-345...
Page 660 OR.W Signed 16-bit SP address offset AAAAAAAAAAAAAAAA A-346 SC140 DSP Core Reference Manual...
Page 661 Restores data register extension pairs, even registers, and loop start registers from the stack. Data register extension pairs are popped the same as even numbered registers. POP Do Restores modifier control, odd registers, and loop counter registers from the stack. SC140 DSP Core Reference Manual A-347...
Page 662 0 e 1 POP Do Note 1: An extra cycle is added if the shadow SP is not valid when the POP instruction is executed. See Section 5.5.4, “Shadow Stack Pointer Registers,” Instruction Fields A-348 SC140 DSP Core Reference Manual...
Page 663 00101 01101 10101 11101 00110 01110 MCTL 10110 11110 00111 D3.E 01111 D7.E 10111 — 11111 — Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. SC140 DSP Core Reference Manual A-349...
Page 664 Note: For proper data register restoration, extensions that were pushed as a pair should be popped as a pair. Extensions pushed as single registers should be popped as single registers. MEMORY LONG WORD La + EXTENSION De (even) Lb + EXTENSION Do (odd) A-350 SC140 DSP Core Reference Manual...
Page 665 1 0 0 1 e e e 1 0 0 1 e 0 1 e 1 POPN Do Note 1: An extra cycle is added if the shadow SP is not valid when the POP instruction is executed. See Section 5.3.3, “Shadow Stack Pointer Registers.” Instruction Fields SC140 DSP Core Reference Manual A-351...
Page 666 00101 01101 10101 11101 00110 01110 MCTL 10110 11110 00111 D3.E 01111 D7.E 10111 — 11111 — Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. A-352 SC140 DSP Core Reference Manual...
Page 667 Pushes data register extension pairs, even registers, and loop start registers onto the current stack. Data register extension pairs are pushed the same as even numbered registers. PUSH Do Pushes modifier control, odd registers, and loop counter registers onto the current stack. SC140 DSP Core Reference Manual A-353...
Page 668 1 0 0 1 E E E 0 0 0 1 E 0 0 E 0 PUSH De 1 0 0 1 e e e 1 0 0 1 e 0 0 PUSH Do A-354 SC140 DSP Core Reference Manual...
Page 669 00101 01101 10101 11101 00110 01110 MCTL 10110 11110 00111 D3.E 01111 D7.E 10111 — 11111 — Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. SC140 DSP Core Reference Manual A-355...
Page 670 Pushes data register extension pairs, even registers, and loop start registers onto the current stack. Data register extension pairs are pushed the same as even numbered registers. PUSHN Do Pushes modifier control, odd registers, and loop counter registers onto the current stack. A-356 SC140 DSP Core Reference Manual...
Page 671 Pops of extensions restore the Ln bit in the destination register. Pops to data registers clear the Ln bit. Example pushn d0.e:d1.e Register/Memory Address Before After $00000008 $000000010 L0:D0 $0:$FF89ABCDEF L1:D1 $0:$0001234567 ($000008) $000000FF SC140 DSP Core Reference Manual A-357...
Page 672 00101 01101 10101 11101 00110 01110 MCTL 10110 11110 00111 D3.E 01111 D7.E 10111 — 11111 — Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used. A-358 SC140 DSP Core Reference Manual...
Page 673 0 . . . 0 0 . . . 0 Scale Down 0 . . . 0 0 . . . 0 Scale Up 0 . . . 0 0 . . . 0 SC140 DSP Core Reference Manual A-359...
Page 674 After rounding $CAFE 80001100 1010 1111 1110 1000 0000 0000 0000 Scaling up is selected in SR[4-5], and 2’s complement rounding is selected in SR[3]. Bit 15 is rounded up because bit 14 = 1. A-360 SC140 DSP Core Reference Manual...
Page 675 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-361...
Page 676 39 in the data register was zero before rotation. Clears the Ln bit in the destination register. Example rol d5 Register/Memory Address Before After $00E4 0000 $00E4 0001 L5:D5 $0:$FF A000 0005 $0:$FF 4000 000A A-362 SC140 DSP Core Reference Manual...
Page 677 1 0 0 1 F F F 1 1 0 0 0 ROL Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-363...
Page 678 0 in the data register was zero before rotation. Clears the Ln bit in the destination register. Example ror d15 Register/Memory Address Before After $00E0 0000 $00E0 0001 L15:D15 $0:$FF A000 0005 $0:$7F D000 0002 A-364 SC140 DSP Core Reference Manual...
Page 679 1 0 0 1 F F F 1 1 0 0 0 ROR Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-365...
Page 680 Register Address Bit Name Description SR[18] Determines which stack pointer used and execution working mode. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[31:0] Restores SR from stack. NMID Enables NMI. A-366 SC140 DSP Core Reference Manual...
Page 681 1 0 0 1 1 1 1 1 0 1 1 1 0 0 1 1 Note 1: The shadow SP is valid or not valid. RTE uses 5 cycles if the shadow SP is valid. RTE uses 6 cycles if the shadow SP is not valid. SC140 DSP Core Reference Manual A-367...
Page 682 Register Address Bit Name Description SR[18] Determines which stack pointer used and execution working mode. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[31:0] Restores SR from stack. NMID Enables NMI. A-368 SC140 DSP Core Reference Manual...
Page 683 SP is not valid. To get the correct cycle count for this instruction, subtract the execution time used by the execution set in the delay slot. The cycle count for this instruction cannot be less than 2 cycles. SC140 DSP Core Reference Manual A-369...
Page 684 SR[18] Determines which stack pointer is used. Status and Conditions Changed by Instruction None. Example Register/Memory Address Before After $00E4 0000 $0000 2008 $0000 2000 ($2000) $0000 0018 $0000 0018 $0000 0026 $0000 0018 A-370 SC140 DSP Core Reference Manual...
Page 685 Note 1: RTS uses 3 cycles if the RAS is valid. RTS uses 5 cycles if the RAS is not valid and the shadow SP is valid. RTS uses 6 cycles if neither the RAS nor the shadow SP are valid. SC140 DSP Core Reference Manual A-371...
Page 686 - - - Execute the $47 to d9 and increment d9 to $48, the instruc- rtsd move.w #$47,d9 tion in the delay slot. Return from the subroutine. PC and inc d9 SR popped from the stack. A-372 SC140 DSP Core Reference Manual...
Page 687 The cycle count for this instruction cannot be less than 1 cycle (2 cycles if shadow SP is not valid). SC140 DSP Core Reference Manual A-373...
Page 688 RTSTK does one 32-bit long-word memory access. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] Determines which stack pointer is used. Status and Conditions Changed by Instruction Register Address Bit Name Description NMID Cleared . A-374 SC140 DSP Core Reference Manual...
Page 689 1 0 0 1 1 1 1 1 0 1 1 1 0 1 0 1 RTSTK Note 1: RTSTK uses 5 cycles if the shadow SP is valid. RTSTK uses 6 cycles if the shadow SP is not valid. SC140 DSP Core Reference Manual A-375...
Page 690 32-bit long-word memory access. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] Determines which stack pointer is used. Status and Conditions Changed by Instruction Register Address Bit Name Description NMID Cleared . A-376 SC140 DSP Core Reference Manual...
Page 691 Note 1: RTSTKD uses 5 cycles if shadow SP is valid. RTSTKD uses 6 cycles if the shadow SP is not valid. To get the correct cycle count for this instruction, subtract the execution time used by the execution set in the delay slot. The cycle count for this instruction cannot be less than 2 cycles. SC140 DSP Core Reference Manual A-377...
Page 692 Bit Name Description Clears the Ln bit in the destination register. EMR[2] DOVF Set if saturation occurs. Example sat.f d2,d3 Register/Memory Address Before After L2:D2 $1:$00 846D 0000 L3:D3 $0:$00 7FFF 0000 $0000 0004 A-378 SC140 DSP Core Reference Manual...
Page 693 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-379...
Page 694 $0:$00 7FFF FFFF $0000 0004 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 F F F 1 1 0 0 1 SAT.L Dn Note: ** indicates serial grouping encoding. A-380 SC140 DSP Core Reference Manual...
Page 695 SAT.L Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-381...
Page 696 31. Example sub d0,d1,d1 sbc d2,d3 Register/Memory Address Before After $00 0000 0008 L1:D1 $0:$00 0000 0005 $0:$FF FFFF FFFD $00E4 0000 $00E4 0001 $00 0000 0003 L3:D3 $0:$00 0000 0005 $0:$00 0000 0001 A-382 SC140 DSP Core Reference Manual...
Page 697 1 0 1 1 e e 0 1 1 1 1 0 1 1 SBC Dc,Dd Note: ** indicates serial grouping encoding. Instruction Fields Dc,Dd Data Register Pairs D0,D1 D2,D3 D4,D5 D6,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-383...
Page 698 (SR [SM] = 1), clears the Ln bit in the destination register. Example sbr d3,d0 Register/Memory Address Before After $00E0 0000 $00 1539 0030 L0:D0 $0:$00 2AE7 0080 $0:$00 15AE 0000 $0000 0000 A-384 SC140 DSP Core Reference Manual...
Page 699 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-385...
Page 700 Clear the active loop flag if the active loop counter is less than or equal to one. Example skipls _label Register/Memory Address Before After $10E0 0000 $00E0 0000 _label (displacement) $0010 $0000 000E $0000 001E A-386 SC140 DSP Core Reference Manual...
Page 701 Note 1: If LC>1, the instruction takes 1 cycle. If LC<=0 and the branch is taken, the instruction takes 4 cycles. Instruction Fields displacement aAAAAAAAAAAAAAAA0 16-bit signed PC relative displacement. The encoding is the displacement with bit 0 stripped and replaced by the sign bit. SC140 DSP Core Reference Manual A-387...
Page 702 Determines execution working mode. Status and Conditions Changed by Instruction None Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 1 1 1 1 0 1 1 1 1 0 0 1 STOP A-388 SC140 DSP Core Reference Manual...
Page 703 Ln bit in the destination register. If in arithmetic saturation mode (SR [SM] = 1), clears the Ln bit in the destination register. Example 1 sub d1,d0,d2 Register/Memory Address Before After $00 0000 0005 $00 0000 0008 $00E4 0000 $00E4 0001 SC140 DSP Core Reference Manual A-389...
Page 704 1 0 1 1 F F F 0 0 SUB Da,Db,Dn 1 0 1 1 F F F 0 1 SUB Db,Da,Dn 1 0 0 0 F F F 1 1 0 0 1 SUB Da,Da,Dn Note: ** indicates serial grouping encoding. A-390 SC140 DSP Core Reference Manual...
Page 705 D7,D7 Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. iiiii 5-bit unsigned immediate data SC140 DSP Core Reference Manual A-391...
Page 706 Register/Memory Address Before After $00 0003 2A14 L1:D1 $0:$FF FFFE 2A18 $0:$FF FFFB 0004 Example 2 sub2 d0,d1 Register/Memory Address Before After $00 7000 8000 L1:D1 $0:$FF 8000 7000 $0:$FF 1000 F000 A-392 SC140 DSP Core Reference Manual...
Page 707 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-393...
Page 708 Address modification bits when updating R0–R7. Otherwise, the instruction is not affected by MCTL. Status and Conditions Changed by Instruction None. Example suba r1,r0 Register/Memory Address Before After MCTL $0000 0000 $0000 0001 $0000 0010 $0000 000F A-394 SC140 DSP Core Reference Manual...
Page 709 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. iiiii 5-bit unsigned immediate data SC140 DSP Core Reference Manual A-395...
Page 710 (SR [SM] = 1), clears the Ln bit in the destination register. Example 1 subl d0,d1 Register/Memory Address Before After $00E0 0000 $00E0 0000 $00 0000 0003 L1:D1 $0:$00 0000 0004 $0:$00 0000 0005 $0000 0000 A-396 SC140 DSP Core Reference Manual...
Page 711 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-397...
Page 712 (SR [SM] = 1), clears the Ln bit in the destination register. Example subnc.w #$15,d0 Register/Memory Address Before After $00E0 0000 $00E0 0000 Immediate $0015 L0:D0 $0:$00 0000 0010 $0:$FF FFFF FFFB $0000 0000 A-398 SC140 DSP Core Reference Manual...
Page 713 1 0 F F F SUBNC.W #s16,Dn 1 0 0 Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. #s16 16-bit signed immediate data iiiiiiiiiiiiiiii SC140 DSP Core Reference Manual A-399...
Page 714 Clears the Ln bit in the destination register. Example 1 sxt.b d3,d0 Register/Memory Address Before After $FF FE34 A086 L0:D0 $0:$FF FFFF FF86 Example 2 sxt.w d3,d2 Register/Memory Address Before After $00 0000 7056 A-400 SC140 DSP Core Reference Manual...
Page 715 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-401...
Page 716 Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None. Example 1 sxta.b r3,r1 Register/Memory Address Before After $0000 2086 $FFFF FF86 Example 2 sxta.w r3 Register/Memory Address Before After $03BC 8A56 $FFFF 8A56 A-402 SC140 DSP Core Reference Manual...
Page 717 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-403...
Page 718 L14:D14 $0:$FF F23A 1422 Example 2 tfr d7,d6 Register/Memory Address Before After $00E0 0020 $00 5000 0000 $1:$00 5000 0000 Scaling up set by SR[5}, so L6 bit is set by bit 30 overflow. A-404 SC140 DSP Core Reference Manual...
Page 719 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-405...
Page 720 AGU Source Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-406 SC140 DSP Core Reference Manual...
Page 721 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-407...
Page 722 Note: The value in NSP or ESP will have the lower three bits equal to zero. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] Determines which stack pointer is used and execution working mode. Status and Conditions Changed by Instruction None A-408 SC140 DSP Core Reference Manual...
Page 723 1 0 0 1 1 0 1 0 0 1 1 1 1 R R R TFRA Rn, OSP Instruction Fields Address Register Note: If registers R8–R15 are accessed instead of R0–R7, a prefix is used. SC140 DSP Core Reference Manual A-409...
Page 724 Note: The Ln bit is re-calculated (not copied) in the destination register. Saturation mode is ignored and no saturation is done. Example tfrt d14,d15 Register/Memory Address Before After $00E4 0002 $FF F23A 1422 L15:D15 $0:$FF F23A 1422 A-410 SC140 DSP Core Reference Manual...
Page 725 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-411...
Page 726 (masking all maskable interrupts). The starting address of the exception processing routine is loaded to the PC and the Exception working mode is entered. TRAP The starting address of the exception processing routine is VBA[31:12]:$000. Status and Conditions that Affect Instruction None. A-412 SC140 DSP Core Reference Manual...
Page 727 $0000 0012 $8000 0000 $00E0 0000 $00E4 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 0 TRAP SC140 DSP Core Reference Manual A-413...
Page 728 1 0 0 1 F F F 1 1 0 1 0 0 1 TSTEQ Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Note: Note: A-414 SC140 DSP Core Reference Manual...
Page 729 Example 1 tsteqa.w r4 Register/Memory Address Before After $5F3E 0000 $00E4 0000 $00E4 0002 Example 2 tsteqa.l r1 Register/Memory Address Before After $0000 0000 $00E4 0000 $00E4 0002 SC140 DSP Core Reference Manual A-415...
Page 730 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. A-416 SC140 DSP Core Reference Manual...
Page 731 1 0 0 1 F F F 1 1 0 1 0 TSTGE Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-417...
Page 732 Set if the source operand is greater than or equal to zero and cleared if the source operand is not greater than or equal to zero. Example tstgea.l r7 Register/Memory Address Before After $57E3 A6CC $00E4 0000 $00E4 0002 A-418 SC140 DSP Core Reference Manual...
Page 733 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-419...
Page 734 1 0 0 1 F F F 1 1 0 1 0 1 0 TSTGT Dn Note: ** indicates serial grouping encoding. Instruction Fields Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. A-420 SC140 DSP Core Reference Manual...
Page 735 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-421...
Page 736 * Words 0, 1, 2, and 3 have different meanings in big and little endian modes, as follows: Memory Address Word Big Endian Mode Little Endian Mode (Rn+2) (Rn) (Rn) (Rn+2) (Rn+6) (Rn+4) (Rn+4) (Rn+6) A-422 SC140 DSP Core Reference Manual...
Page 737 Viterbi flag VF3. If the Viterbi flag VF3 is set, then the left-shifted D3.H is chosen. Otherwise, the left-shifted D1.H is chosen and the LSB is filled with one. The address register values used with this instruction must be long word-aligned (a multiple of 4). SC140 DSP Core Reference Manual A-423...
Page 738 Register/Memory Address Before After (Little Endian) After (Big Endian) MCTL $0000 0000 $00e4 0000 $00 2A62 EA79 $00 5437 9EAC $0000 0002 $0000 0060 $0000 0068 $0000 0068 $0060 $D4F2 $D4F3 $0062 $D4F3 $D4F2 A-424 SC140 DSP Core Reference Manual...
Page 739 1 1 0 0 1 0 1 0 0 0 1 1 0 R R R VSL.2F D1:D3,(Rn)+N0 Instruction Fields Address Register Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-425...
Page 740 A non-maskable interrupt is asserted. Exit the WAIT state and service the non-maskable interrupt immediately after the execution set that included the WAIT instruction, regardless of the value of the IPL and DI bits in A-426 SC140 DSP Core Reference Manual...
Page 741 Determines execution working mode. Status and Conditions Changed by Instruction None Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 1 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 WAIT SC140 DSP Core Reference Manual A-427...
Page 742 Clears the Ln bit in the destination register. Example 1 zxt.b d2,d5 Register/Memory Address Before After $00 46EA 8BE8 L5:D5 $0:$00 0000 00E8 Example 2 zxt.w d3,d6 Register/Memory Address Before After $FF A836 5EC4 A-428 SC140 DSP Core Reference Manual...
Page 743 Instruction Fields Single Source Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register Note: This instruction can specify D8-D15 as operands by using a prefix. SC140 DSP Core Reference Manual A-429...
Page 744 Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None. Example 1 zxta.b r3,n2 Register/Memory Address Before After $E4A6 5C8A $0000 008A Example 2 zxta.w r4 Register/Memory Address Before After $E4A6 5C8A $0000 5C8A A-430 SC140 DSP Core Reference Manual...
Page 745 AGU Source/Destination Register 0000 0100 — 1000 1100 0001 0101 — 1001 1101 0010 0110 — 1010 1110 0011 0111 1011 1111 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SC140 DSP Core Reference Manual A-431...
Page 746 ZXTA.x A-432 SC140 DSP Core Reference Manual...
Page 747: B.1 Using The Starcore Registry
The following table lists current assignments of REVNO and CORETP. The Tools column lists the first version of StarCore software development tools to support the listed Instruction Set Version. SC140 DSP Core Reference Manual...
Page 748: Scid Assignments
REVNO. Software tools developers and run-time software need to be aware of the actual CORETP software migration issues. For historical reasons, the CORETP field of the Rainbow product is 000 instead of 001. However the SW tools should consider this product as identical with the MCS8101 rev0 product. SC140 DSP Core Reference Manual...
Page 749 Index ASLA A-51 ASLL A-52 AAU (address arithmetic unit) 1-3 ASLW A-55 ABS A-20 ASR A-57 Accelerator 2-5 6-57 ASRA A-59 Access width support 2-42 ASRR A-60 ADC A-22 ASRW A-63 ADD A-24 ATS (access type selection) 4-56 4-60 ADD2 A-27 AWS (access width selection) 4-59 ADDA A-29 ADDL1A A-32...
Page 750: Conditional
CCS (comparator condition selection bits) 4-60 Debug mode 4-11 Change-of-flow instructions 2-68 DEBUGERST (debugger status information) 4-42 CLB A-113 DEBUGEV A-138 CLR A-115 Debugging system 4-1 CMPEQ A-117 DECA A-139 CMPEQ.W A-119 DECEQ A-141 CMPEQA A-121 DECEQA A-143 CMPGT A-123 DECGE A-144 CMPGT.W A-125 DECGEA A-146...
Page 751 CS 4-55 ILST 3-9 EDCAEN 4-55 NMID 3-8 EDCAST5-0 (EDCA #5-0 status) 4-42 Emulation and debug 4-1 EDCD (data event detection channel) 4-24 4-58 Endian support 2-56 control register (EDCD_CTRL) 4-58 bit mask instructions 2-67 mask register (EDCD_MASK) 4-61 change-of-flow instructions 2-68 control instructions 2-68 reference value register (EDCD_REF) 4-61 EDCD_CTRL (EDCD control register) 4-58...
Page 752 ESEL_DTB (ES mask disable trace register) 4-26 4-65 Grouping Mechanism 5-6 ESEL_ETB (ES mask enable trace register) 4-26 4-64 ESP (exception stack pointer register) 2-35 ESR (EOnCE status register) 4-37 I2-0 (interrupt mask bits) 3-3 CORES 4-38 IADDNC.W A-175 CORETP 4-39 IFc A-176 DRCOUNTER 4-40 ILIN (illegal instruction) 3-9...
Page 753 BMSET.W A-82 IMPYSU A-193 BMTSET A-84 IMPYUU A-195 BMTSET.W A-86 INC A-197 BMTSTC A-89 INC.F A-199 BMTSTC.W A-91 INCA A-201 BMTSTS A-94 INSERT A-203 JF A-205 BMTSTS.W A-96 BRA A-99 JFD A-207 BRAD A-101 JMP A-209 BREAK A-103 JMPD A-211 BSR A-105 JSR A-213 BSRD A-107...
Page 754 NOT.W A-338 OR A-340 A-342 JF A-205 OR.W A-344 JFD A-207 POP A-347 JMP A-209 POPN A-350 JMPD A-211 PUSH A-353 JSR A-213 PUSHN A-356 JSRD A-215 RND A-359 JT A-217 ROL A-362 JTAG 5-44 5-45 ROR A-364 JTAG access 4-33 RTE A-366 JTAG and EOnCE interface 4-2 RTED A-368...
Page 755 MIN A-253 Modifier registers (M0-M3) 2-36 PAB (program address bus) 2-1 Modulo adder 2-33 PAG (program address generator) 2-5 Modulo addressing 2-4 PC (program counter) 1-3 Modulo addressing mode 2-45 PC relative addressing modes 2-40 Move instructions 2-51 2-52 PC relative mode 2-40 fractional moves 2-54 PC_DETECT (PC breakpoint detection register) 4-49 integer moves 2-53...
Page 756 RM (rounding mode bit) 3-5 SM 3-6 RND A-359 T 3-6 ROL A-362 VF3-0 3-4 ROR A-364 SRAM (static random access memory) 1-2 Rounding 2-21 2-23 Stack pointer registers 2-4 RTE A-366 Stack support 5-32 fast call-return from subroutines 5-36 RTED A-368 RTS A-370 instructions 2-67...
Page 757 Trace unit control register (TB_CTRL) 4-65 read pointer register (TB_RD) 4-69 register set 4-30 virtual register (TB_BUFF) 4-69 write pointer register (TB_WR) 4-69 TRAP 5-37 A-412 TRSINT (transmit interrupt) 4-41 TRSMT (transmit) 4-38 TRST (test reset pin) 4-2 True bit 3-6 TSTEQ A-414 TSTEQA.x A-415 TSTGE A-417...
Page 758 I-10 Index...
Page 759 SC140 DSP Core Reference Manual...

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Freescale Semiconductor SC140 DSP Core Reference Manual

About this Book

Chapter 1 Introduction

Chapter 2 Core Architecture

Chapter 3 Control Registers

Chapter 4 Emulation and Debug (Eonce)

Chapter 5

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