Page 1 DSP56374 24-Bit Digital Signal Processor User Guide Document Number: DSP56374UG Rev. 1.2 07/2007...
Page 2 “Typicals”, must be validated for each customer application by customer’s technical experts. www.freescale.com/support Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Europe, Middle East, and Africa: Freescale Semiconductor products are not designed, intended, or authorized for use as components...
Page 3: Table Of Contents
Paragraph Page Number Number Preface i Chapter 1 DSP56374 Overview Introduction ................................1-1 DSP56300 Core Description .............................1-2 DSP56374 Audio Processor Architecture .........................1-3 DSP56300 Core Functional Blocks ...........................1-3 1.4.1 Data ALU ................................1-3 1.4.1.1 Data ALU Registers ............................1-3 1.4.1.2 Multiplier-Accumulator (MAC) ........................1-3 1.4.2 Address Generation Unit (AGU) ........................1-4...
Page 4 Clock Generator ................................5-6 5.5.1 Low-Power Divider (LPD) ..........................5-6 Operating Frequency (Fosc) ............................5-6 PLL Programming Model ............................5-7 PLL Initialization Procedure ...........................5-10 PLL Programming Examples ..........................5-11 Chapter 6 General Purpose Input/Output Introduction ................................6-1 Programming Model ..............................6-1 DSP56374 Users Guide, Rev. 1.2 TOC-2 Freescale Semiconductor...
Page 5 HCSR Reserved Bits—Bits 23, 18 and 16 ....................7-10 7.4.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17 ..................7-10 7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19 ....................7-10 7.4.6.17 Host Receive Overrun Error (HROE)—Bit 20 ...................7-11 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor TOC-3...
Page 6 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23 ............8-9 8.3.2 ESAI Transmit Control Register (TCR) ......................8-9 8.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0 ....................8-10 8.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1 ....................8-10 DSP56374 Users Guide, Rev. 1.2 TOC-4 Freescale Semiconductor...
Page 7 SAICR Serial Output Flag 0 (OF0) - Bit 0 ....................8-23 8.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1 ....................8-24 8.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2 ....................8-24 8.3.5.4 SAICR Reserved Bits - Bits 5-3, 23-9 ......................8-24 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor TOC-5...
Page 8 Port E Data register (PDRE) ........................8-37 ESAI Initialization Examples ..........................8-38 8.6.1 Initializing the ESAI Using Individual Reset ....................8-38 8.6.2 Initializing Just the ESAI Transmitter Section ....................8-38 8.6.3 Initializing Just the ESAI Receiver Section ......................8-38 DSP56374 Users Guide, Rev. 1.2 TOC-6 Freescale Semiconductor...
Page 9 Watchdog Counter & WCNTR Register ......................10-2 10.4.3 Watchdog Modulus Register (WMR) ......................10-3 10.4.4 Watchdog Service Register (WSR) ........................10-3 10.5 Operation in Different Modes ..........................10-3 10.5.1 WAIT Mode ..............................10-3 10.5.2 DEBUG Mode ..............................10-3 10.5.3 STOP MODE ..............................10-3 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor TOC-7...
Page 10 Programming Sheets ............................C-1 C.1.5 Internal I/O Memory Map ..........................C-1 C.1.6 Interrupt Vector Addresses ..........................C-7 Interrupt Source Priorities (within an IPL) ......................C-10 Programming Sheets ...............................C-11 Appendix D BSDL 52-pin BSDL ................................D-1 80-pin BSDL ................................D-6 DSP56374 Users Guide, Rev. 1.2 TOC-8 Freescale Semiconductor...
Page 11 ESAI Frame Sync Generator Functional Block Diagram ..................8-8 TCR Register ................................8-10 Normal and Network Operation ..........................8-13 Frame Length Selection ............................8-15 RCCR Register ................................8-17 RCR Register ................................8-20 8-10 SAICR Register ...............................8-23 8-11 SAICR SYN Bit Operation .............................8-25 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor LOF-1...
Page 12 ESAI Receive Clock Control Register ........................C-21 C-11 ESAI Receive Control Register ..........................C-22 C-12 ESAI Common Control Register ..........................C-23 C-13 ESAI Status Register ..............................C-24 C-14 ESAI_1 Transmit Clock Control Register ......................C-25 C-15 ESAI_1 Transmit Control Register ........................C-26 DSP56374 Users Guide, Rev. 1.2 LOF-2 Freescale Semiconductor...
Page 13 Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR) ..............C-31 C-21 Timer Control/Status Register ..........................C-32 C-22 Timer Load, Compare and Count Registers ......................C-33 C-23 GPIO Port C ................................C-35 C-24 GPIO Port E ................................C-36 C-25 GPIO Port G ................................C-37 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor LOF-3...
Page 14: Freescale Semiconductor
List of Figures Notes DSP56374 Users Guide, Rev. 1.2 LOF-4 Freescale Semiconductor...
Page 15: List Of Tables
List of Tables Table Page Number Number DSP56374 Memory Switch Configurations ......................1-2 DSP56374 Functional Signal Groupings ........................2-1 Power Inputs ................................2-1 Grounds ..................................2-3 SCAN signals ................................2-4 Clock and PLL Signals ..............................2-4 Interrupt and Mode Control ............................2-4 Serial Host Interface Signals .............................2-6 Enhanced Serial Audio Interface Signals ........................2-8...
Page 16: Freescale Semiconductor
Timer Control/Status Register (TCSR) Bit Definitions ..................9--21 Inverter (INV) Bit Operation ...........................9-24 Internal I/O Memory Map (X Memory) ........................C-1 Internal I/O Memory Map (Y Memory) ........................C-4 DSP56374 Interrupt Vectors ............................C-7 Interrupt Sources Priorities Within an IPL ......................C-10 DSP56374 Users Guide, Rev. 1.2 LOT-2 Freescale Semiconductor...
Page 17 This manual describes the DSP56374 24-bit digital signal processor (DSP), its memory, operating modes and peripheral modules. The DSP56374 is a member of the DSP56300 family of programmable CMOS DSPs. Changes in core functionality specific to the DSP56374 are also described in this manual.
Page 18: Freescale Semiconductor
Appendix B—Equates Lists equates for the DSP56374. Appendix C—Programming Reference Lists peripheral addresses, interrupt addresses and interrupt priorities for the DSP56374. Contains programming sheets listing the contents of the major DSP56374 registers for programmer reference. Appendix D—BSDL Provides the BSDL data for the DSP56374.
Page 19: Revision History
• In Equates statements, corrected addresses for PDRG, PRRG, PCRG on page B-4. Appendix C • In Figure C-24, corrected register addresses for PCRG, PRRG, PDRG. • In Table C-2, corrected register acronyms for PCRG, PRRG, PDRG. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 20: Manual Conventions
The word “reset” is used in four different contexts in this manual: the reset signal, written as “RESET,” the reset instruction, written as “RESET,” the reset operating state, written as “Reset,” and the reset function, written as “reset.” DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 21: Dsp56374 Overview
Introduction The DSP56374 is designed to support a multitude of digital signal processing applications requiring a lot of horsepower in a small package. This manual describes the DSP56374 24-bit digital signal processor (DSP), its memory, operating modes and peripheral modules.
Page 22: Dsp56300 Core Description
DSP56300 Core Description DSP56300 Core Description The DSP56374 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides several times the performance of Freescale’s (formerly Motorola’s) popular DSP56000 core family while retaining code compatibility. The DSP56300 core family offers a new level of performance in speed and power, provided by its rich instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications and multimedia products.
Page 23: Dsp56374 Audio Processor Architecture
80-pin and 52-pin plastic LQFP packages. DSP56374 Audio Processor Architecture This section defines the DSP56374 audio processor architecture. The audio processor is composed of the following units: • The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller, DMA Controller, Memory Module Interface, Peripheral Module Interface and the On-Chip Emulator (OnCE).
Page 24: Address Generation Unit (Agu)
The PCU also includes a hardware system stack (SS). 1.4.4 Internal Buses To provide data exchange between blocks, the following buses are implemented: • Peripheral input/output expansion bus (PIO_EB) to peripherals • Program memory expansion bus (PM_EB) to program memory DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 25: Direct Memory Access (Dma)
Memory cannot be expanded off-chip. There is no external memory bus. 1.4.9 Power Requirements To prevent a high current condition and damage to the DSP upon power up, the 3.3V source must be applied ahead of the 1.25V source as shown below. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 26: Peripheral Overview
General Purpose Input/Output (GPIO) The 80-pin DSP56374 provides 15 dedicated GPIO and 29 programmable pins that can operate either as GPIO pins or peripheral pins (ESAI, ESAI_1 and TEC). The four MOD pins, as well as the SHI HREQ pin, can also be utilized as GPIO. The ESAI and ESAI_1 pins are configured as GPIO after hardware reset.
Page 27: Enhanced Serial Audio Interface (Esai)
Software must periodically service the watchdog timer in order to restart the count down . For more information on the WDT, refer to Chapter 10, Watchdog Timer Module. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 28 DSP56374 Overview Notes DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 29: Signal/Connection Descriptions
2-1. The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V. A special notice for this feature is added to the signal descriptions of those inputs. Resistor values for pins with pull up or pull down resistors may vary with lot and will be between 40k ohms and 65k ohms.
Page 30: Pin Vdd Connections
Core_Vdd Core_Gnd Core_Gnd GPIO_PG10 SDO1_1_PE10 GPIO_PG9 SDO0_1_PE11 HREQ_PH4 PINIT_NMI SS_HA2 IO_Vdd SCK_SCL XTAL MISO_SDA EXTAL MOSI_HA0 PLLD_Vdd GPIO_PG8 PLLD_Gnd GPIO_PG7 PLLP_Gnd IO_Gnd PLLP_Vdd 1.25 V Filter 3.3 V Figure 2-1. 80-pin Vdd Connections DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 31: Ground
SHI, ESAI, ESAI_1, WDT and Timer I/O Ground—IO_GND is the ground for the SHI, ESAI, ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 32: Scan
This pin has an internal pull-up resistor. This input is 5 V tolerant. Input, Output, Port H0—When the MODA/IRQA is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. Disconnected DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 33 MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This pin has an internal pull-up resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 34: Serial Host Interface
This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This pin has an internal pull-up resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 35 Port H4—When HREQ is configured as GPIO, this signal is individually Input, Output, programmable as input, output, or internally disconnected. This pin has an internal pull-up resistor. Disconnected This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 36: Enhanced Serial Audio Interface
Port C5—When the ESAI is configured as GPIO, this Disconnected signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull-up resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 37 Port C4—When the ESAI is configured as GPIO, this Disconnected signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 38 Disconnected signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 2-10 Freescale Semiconductor...
Page 39 Disconnected signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 2-11...
Page 40: Enhanced Serial Audio Interface_1
Disconnected signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 2-12 Freescale Semiconductor...
Page 41 Disconnected signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 2-13...
Page 42 Disconnected signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant DSP56374 Users Guide, Rev. 1.2 2-14 Freescale Semiconductor...
Page 43 Disconnected signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 2-15...
Page 44: Dedicated Gpio - Port G
This input is 5 V tolerant Input, Output, or GPIO Port G6—This signal is individually programmable as input, Disconnected Disconnected output, or internally disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant DSP56374 Users Guide, Rev. 1.2 2-16 Freescale Semiconductor...
Page 45 PG14 Input, Output, or GPIO Port G14—This signal is individually programmable as input, Disconnected Disconnected output, or internally disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 2-17...
Page 46: Timer
PLL enabled and locked and de-asserted when the PLL enabled and unlocked. This pin is also asserted high when the PLL is disabled. This pin has an internal pull-down resistor. This input is 5 V tolerant DSP56374 Users Guide, Rev. 1.2 2-18 Freescale Semiconductor...
Page 47: Jtag/Once Interface
Test Mode Select—TMS is an input signal used to sequence the test controller’s state machine. TMS is sampled on the rising edge of TCK. This pin has an internal pull-up resistor. This input is 5 V tolerant. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 2-19...
Page 48 Signal/Connection Descriptions Notes DSP56374 Users Guide, Rev. 1.2 2-20 Freescale Semiconductor...
Page 49: Memory Configuration
YROM - 4k words. The on-chip memory configuration of the DSP56374 is affected by the state of the MSW0, MSW1 and MS (Memory Switch) control bits in the OMR register in the Status Register. The internal data and program memory configurations are shown in Table 3-7.
Page 50: Default Memory Map (Ms 0)
$FF0000 $FF0000 External External External $005000 $005000 4k ROM 4k ROM $002800 $004000 $004000 $001000 $001000 4k RAM 4k RAM 10k RAM $000000 $000000 $000000 Figure 3-2. Memory Map (MS 1, MSW(1-0) 11) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 51: Memory Map (Ms 1, Msw(1-0) 10)
Y Data ROM 4k Words 20k Words 8k Words 4k Words 6k Words 4k Words $000000 - $FF0000 - $000000 - $001FFF $004000 - $000000 - $004000 - $000FFF $FF4FFF $004FFF $004FFF $0017FF DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 52: Memory Map (Ms 1, Msw(1-0) 01)
$FF0000 $FF0000 External External External $005000 $005000 4k ROM 4k ROM $004000 $004000 $000800 $002800 $001800 10k RAM 6k RAM 2k RAM $000000 $000000 $000000 Figure 3-5. Memory Map (MS 1, MSW(1-0) 00) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 53: Reserved Memory Spaces
The DSP56374 is not capable of directly accessing external memory. 3.1.5 DMA and Memory Memory on the DSP56374 consists of 4 - 1k-word blocks, 5 - 2k-word blocks, and 1 - 4k word block (see Figure 3-1). It is important to understand that the DMA is designed for operation on 1k-word blocks.
Page 54: Memory Blocks
ROM location P:$fff000. Also, when the program control unit fetches an instruction from P:$fff001, instruction 2 (bset #1,a) will be fetched instead. Also, when the program control unit fetches an instruction from P:$fff003, instruction 3 (bset #2,a) will be fetched instead. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 55: Internal I/O Memory Map
Internal I/O Memory Map The DSP56374 on-chip peripheral modules have their register files programmed to the addresses in the internal X-I/O memory range (the top 128 locations of the X data memory space) and internal Y-I/O memory range (48 locations of the Y data memory space) as shown in Table Table C-2.
Page 56 Internal I/O Memory Map DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 57: Core Configuration
4-2. The operating modes are latched from MODA, MODB, MODC and MODD pins during reset. Each operating mode is briefly described below. The operation of all modes is defined by the Bootstrap ROM source code in Appendix A, Bootstrap Source Code. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 58 Operating Modes Table 4-2. DSP56374 Operating Modes Reset Mode MODD MODC MODB MODA Description Vector $000000 Reserved $FF0000 Reserved $FF0000 Jump to PROM starting address (slave SPI mode) $FF0000 Reserved $FF0000 Reserved $FF0000 Bootstrap from SHI (slave SPI mode) $FF0000 Bootstrap from SHI (slave I...
Page 59: Interrupt Priority Registers
Appendix A, Bootstrap Source Code for details on using this boot mode. Interrupt Priority Registers There are two interrupt priority registers in the DSP56374: IPR-C is dedicated for DSP56300 Core interrupt sources. IPR-P is dedicated for DSP56374 Peripheral interrupt sources.
Page 60: Dma Request Sources
DMA transfers. The DMA request sources may be the internal peripherals or external devices requesting service through the IRQA, IRQB, IRQC and IRQD pins. The DMA Request Sources are shown in Table 4-5. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 61: Pll Initialization
10111 Reserved 11000 Reserved 11001-11111 Reserved PLL Initialization The following figure displays the PLL control register (PCTL). This register is used to control the PLL operation including its multiplication/divide factors and enabling bits. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 62: Pll Pre-Divider Factor (Pd0-Pd4)
The DSP56374 PLL Feedback Multiplier is set to 2 during hardware reset, i.e., OD1 is cleared ($0) in the PLL Control Register (PCTL). 4.6.4 PLL Output Divide Factor (OD0-OD1) The DSP56374 PLL Output Divider factor is set to 2 during hardware reset, i.e., OD1 is cleared ($0) and OD0 is set ($1) in the PLL Control Register (PCTL). 4.6.5 PLL Divider Factor (DF0-DF2) The DSP56374 PLL Divider factor is set to 1 during hardware reset, i.e., the Divider Factor Bits DF0-DF2 in the PLL Control Register (PCTL)
Page 63 JTAG Identification (ID) Register Table 4-7. JTAG Identification Register Configuration Version Customer Part Sequence Manufacturer Information Number Number Identity 0000 000111 0000000011 00000001110 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 64 JTAG Identification (ID) Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 65: Pll And Clock Generator
Introduction The DSP56374 core features a Phase Locked Loop (PLL) clock generator in its central processing module. The PLL operation is controlled by a PLL control register (PCTL). The PLL allows the processor to operate at a high internal clock frequency derived from a low-frequency clock input, a feature that offers two immediate benefits.
Page 66: Frequency Predivider
5-2. Note that the PLL will not lose lock when OD0 is changed since OD0 is not in the PLL loop. The PLL will lose lock, however, when OD1 is changed. Also, note that the output divide factor (OD) should not be programmed such that both OD0 = 0 and OD1 = 0. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 67: Pll Multiplication Factor (Mf)
PLL loop, effectively applying a feedback multiplier of 4. Note that, since OD1 is in the closed loop of the PLL, changes to OD1 do cause a loss of lock condition. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 68: Pll Output Frequency (Pll Out)
PLL, changes to OD0 do not cause a loss of lock condition. The figures below show how the OD [1-0] bits affect the PLL Output frequency by dividing the VCO Output. Figure 5-5 displays how setting OD1 = 0 and OD0 = 1 divides the VCO output to generate a PLL Output that is VCO Out/2 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 69: Pll Out = Vco Out/2 [Od1 = 0, Od0 = 1]
Figure 5-6. PLL Out = VCO Out/2 [OD1 = 1, OD0 = 0] Figure 5-7 displays how setting OD1 = 1 and OD0 = 1 divides the VCO output to generate a PLL Output that is VCO Out/4. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 70: Clock Generator
(PEN = 0, PLL disabled), which generates the device frequency from the EXTAL clock directly. Fextal Fosc --------------- - • PLL Output (PEN = 1, PLL enabled), which generates a device frequency defined by the following formula: DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 71: Pll Programming Model
PCTL control bits. The PCTL bits are described in Table 5-3. PLKM PSTP Reset: Reset: The reset value of the PEN bit is based on the value of the PLL PINIT input. Figure 5-9. PLL Control (PCTL) Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 72 Note that OD0 and OD1 should not simultaneously be cleared. The resulting Fosc frequency will exceed the maximum operating frequency when in this case. The PLL Output is defined by the following formula when OD = 1: VCO Out ------------------------- - DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 73 (for example, to enter a low-power mode) should be made by changing the value of the DF[2–0] bits rather than changing the MF[7–0] bits. DF[2–0] DF Value = 16 = 32 = 64 = 128 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 74: Pll Initialization Procedure
PLL Initialization Procedure The DSP56374 PLL is programmed via the PCTL register. Unlike the DSP56371, the DSP56374 does not require a two step initialization process. However, the DSP56374 PLL is backwards compatible with the DSP56371 and will support the two step initialization process. The following programming example illustrates the initialization process.
Page 75: Pll Programming Examples
EXTAL Fosc (MHz) OD1 OD0 FM MF (MHz) Output PCTL (MHz) (MHz) 5 MHz - 20 MHz 300 - 600 MHz (MHz) 27.00 576.0 144.0 $23E010 27.0 6.75 594.0 148.5 148.5 $24E016 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 5-11...
Page 76 11.2896 5.6448 587.0592 146.7648 146.764 $22E01A NOTE The default PLL setting ($04601D) established upon reset when the PINIT pin is pulled high should not be used at or below 150 MHz operation. DSP56374 Users Guide, Rev. 1.2 5-12 Freescale Semiconductor...
Page 77: General Purpose Input/Output
Introduction The DSP56374 provides up to 47 programmable signals that are dedicated GPIO pins or pins that can operate either as GPIO pins or peripheral pins (ESAI, ESAI_1, and TEC). Up to 20 pins can be programmed as signal or GPIO pins in the 52-pin package. The signals (except for MODA - MODD, and HREQ) are configured as GPIO after hardware reset.
Page 78: Port G Data Register (Pdrg)
ESAI/EXTAL clock bits optionally direct the EXTAL clock to the ESAI clocking chain for generating the corresponding high frequency clock, bit clock and framesync clock. There are 8 ESAI/EXTAL clock control bits as described in Table 6-2. These bits are cleared upon reset. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 79: Port H Signals And Registers
GPIO pins. Table 6-3. describes the port-pin configurations. Hardware and software reset sets all PRRH bits. Table 6-3. PCRH and PRRH Bits Functionality PDH[i] PH[i] Port Pin[i] Function Disconnected GPIO input DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 80: Port H Data Register (Pdrh)
PH[i] bit reflects the value present on this pin. If a port pin [i] is configured as a GPIO output, the value written into the corresponding PH[i] bit is reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PH[i] bit is not reset and contains undefined data. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 81: Timer/Event Counter Signals
The timer/event counter signals (TIO0, TIO1 and TIO2), when not used as timer signals can be configured as GPIO signals. These signals are controlled by the appropriate timer control status register (TCSR). The register is described in Chapter 9, Triple Timer Module DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 82 Programming Model DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 83: Serial Host Interface
SHI for communication and data transfer with the DSP through a shift register that may be accessed serially using either the or the SPI bus protocols. Figure 7-1 shows the SHI block diagram. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 84: Shi Clock Generator
Section 7.4.1, SHI Input/Output Shift Register (IOSR)—Host Side DSP side • —see Figure 7-4 Section 7.4.2, SHI Host Transmit Data Register (HTX)—DSP Side through Section 7.4.6, SHI Control/Status Register (HCSR)—DSP Side for detailed information. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 85: Shi Programming Model—Host Side
Figure 7-3. SHI Programming Model—Host Side Figure 7-4. SHI Programming Model—DSP Side The SHI interrupt vector table is shown in Table 7-1 and the exception priorities generated by the SHI are shown in Table 7-2. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 86: Shi Input/Output Shift Register (Iosr)-Host Side
DSP core instructions or by DMA transfers clears the HTDE flag. The DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set (see Section 7.4.6.10, HCSR Transmit-Interrupt Enable (HTIE)—Bit 11). Data should not be written to the HTX DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 87: Shi Host Receive Data Fifo (Hrx)-Dsp Side
The CPHA bit is set and the CPOL bit is cleared during hardware reset and software reset. The programmer may select any of four combinations of serial clock (SCK) phase and polarity when operating in the SPI mode (See Figure 7-6). DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 88: Hckr Prescaler Rate Select (Hrs)-Bit 2
HCKFR is set. The HRS bit is cleared during hardware reset and software reset. NOTE Use the equations in the SHI data sheet to determine the value of HRS for the specific serial clock frequency required. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 89: Hckr Divider Modulus Select (Hdm[7:0])-Bits 10-3
The HCKR and the HCSR control bits are not affected when HEN is cleared. When operating in master mode, HEN should be cleared only when the SHI is idle (HBUSY = 0). HEN is cleared during hardware reset and software reset. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 90: Shi Individual Reset
It is recommended that an SHI individual reset be generated (HEN cleared) before changing HMST. HMST is cleared during hardware reset and software reset. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 91: Hcsr Host-Request Enable (Hrqe[1:0])-Bits 8-7
HTIE and the RTI instruction at the end of the interrupt service routine. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 92: Hcsr Receive Interrupt Enable (Hrie[1:0])-Bits 13-12
The read-only status bit HRFF indicates, when set, that the Host Receive FIFO (HRX) is full. HRFF is cleared when HRX is read by the DSP (read instructions or DMA transfers) and at least one place is available in the FIFO. HRFF is cleared by hardware reset, software reset, SHI individual reset and during the stop state. DSP56374 Users Guide, Rev. 1.2 7-10 Freescale Semiconductor...
Page 93: Host Receive Overrun Error (Hroe)-Bit 20
During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line when the clock line is high are interpreted as control signals (see Table 7-7). DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 7-11...
Page 94 In this case the transmitter must leave the data line high to enable the master to generate the stop event. Handshaking may also be accomplished by using the clock synchronizing mechanism. Slave devices DSP56374 Users Guide, Rev. 1.2 7-12...
Page 95: I 2 C Data Transfer Formats
SCK/SCL is the SCK serial clock input. • MISO/SDA is the MISO serial data output. • MOSI/HA0 is the MOSI serial data input. • SS/HA2 is the SS slave select input. • HREQ is the Host Request output. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 7-13...
Page 96: Spi Master Mode
MISO/SDA is the SDA open drain serial data line. • MOSI/HA0 is the HA0 slave device address input. • SS/HA2 is the HA2 slave device address input. • HREQ is the Host Request output. DSP56374 Users Guide, Rev. 1.2 7-14 Freescale Semiconductor...
Page 97: Receive Data In I C Slave Mode
C master mode, the SHI external pins operate as follows: • SCK/SCL is the SCL open drain serial clock output. • MISO/SDA is the SDA open drain serial data line. • MOSI/HA0 is the HA0 slave device address input. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 7-15...
Page 98: Receive Data In I 2 C Master Mode
If both IOSR and HTX are empty, the SHI suspends the serial clock until new data is written into HTX (when the SHI proceeds with the transmit session) or HIDLE is set (the SHI reactivates the clock to generate the stop event and terminate the transmit session). DSP56374 Users Guide, Rev. 1.2 7-16...
Page 99: Shi Operation During Dsp Stop
It is recommended that the SHI be disabled before entering the stop state. 7.7.6 GPIO- HREQ Signal and Registers Note that the HREQ pin can also be programmed as a GPIO. See Section 6.2.3, Port H Signals and Registers. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 7-17...
Page 100 Serial Host Interface Notes DSP56374 Users Guide, Rev. 1.2 7-18 Freescale Semiconductor...
Page 101: Enhanced Serial Audio Interface (Esai)
It is a superset of the 56300 Family ESSI peripheral and of the 56000 Family SAI peripheral. NOTE There are two independent and identical ESAIs in the DSP56374:ESAI and ESAI_1. For simplicity, a single generic ESAI is described here.
Page 102: Esai Data And Control Pins
2 to 5 with receivers 0 to 3. The actual mode of operation is selected under software control. All transmitters operate fully synchronized under control of the same transmitter clock signals. All receivers operate fully synchronized under control of the same receiver clock signals. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 103: Serial Transmit 0 Data Pin (Sdo0)
If a data word follows immediately, there is no high-impedance interval. SDO5/SDI0 may be programmed as a general-purpose I/O pin (PC6) when the ESAI SDO5 and SDI0 functions are not being used DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 104: Receiver Serial Clock (Sckr)
TCKD bit in the TCCR register. The SCKT is a clock input or output used by all the enabled transmitters in the asynchronous mode (SYN=0) or by all the enabled transmitters and receivers in the synchronous mode (SYN=1) (see Table 8-2). DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 105: Frame Sync For Receiver (Fsr)
IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. FSR may be programmed as a general-purpose I/O pin (PC1) when the ESAI FSR function is not being used. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 106: Frame Sync For Transmitter (Fst)
TPM0 THCKD TFSD TCKD THCKP TFSP TCKP TFP3 TFP2 TFP1 TFP0 TDC4 TDC3 Figure 8-2. TCCR Register The ESAI TCCR register is located at x:$FFFFB6. The ESAI_1 TCCR register is located at y:$FFFF96. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 107: Tccr Transmit Prescale Modulus Select (Tpm7-Tpm0) - Bits 7-0
Notes: Section 6.2.2.4, ESAI/EXTAL Clocking Control 1.ETIx, ETOx, ERIx and EROx bit descriptions are covered in 2. Fosc is the DSP56300 Core internal clock frequency. Figure 8-3. ESAI Clock Generator Functional Block Diagram DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 108: Tccr Transmit Prescaler Range (Tpsr) - Bit 8
TFP3-TFP0 bits specify an additional division ratio in the clock divider chain. See Table 8-3 for the specification of the divide ratio. The ESAI high frequency clock generator functional diagram is shown in Figure 8-3. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 109: Tccr Transmit Clock Polarity (Tckp) - Bit 18
The read/write Transmit Control Register (TCR) controls the ESAI transmitter section. Interrupt enable bits for the transmitter section are provided in this control register. Operating modes are also selected in this register.See Figure 8-5. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 110: Tcr Esai Transmit 2 Enable (Te2) - Bit 2
During that time period, the SDO2/SDI3 pin remains in the high-impedance state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE2 can be left enabled. DSP56374 Users Guide, Rev. 1.2 8-10...
Page 111: Tcr Esai Transmit 3 Enable (Te3) - Bit 3
If the data word is right-aligned (TWA=1), and zero padding is disabled (PADC=0), the first data bit is repeated before the transmission of the data word. If zero padding is enabled (PADC=1), zeroes are transmitted before the transmission of the data word. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 8-11...
Page 112: Tcr Transmit Network Mode Control (Tmod1-Tmod0) - Bits 9-8
16 bits long, and the next 12 slots and words will be 20 bits long, as required by the AC97 protocol. Table 8-4. Transmit Network Mode Selection TMOD1 TMOD0 TDC4-TDC0 Transmitter Network Mode $0-$1F Normal Mode On-Demand Mode $1-$1F Network Mode Reserved AC97 DSP56374 Users Guide, Rev. 1.2 8-12 Freescale Semiconductor...
Page 113: Tcr Tx Slot And Word Length Select (Tsws4-Tsws0) - Bits 14-10
The possible combinations are shown in Table 8-5. See also the ESAI data path programming model in Figure 8-13 Figure 8-14. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 8-13...
Page 114: Tcr Transmit Frame Sync Length (Tfsl) - Bit 15
The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL is set, a 1-bit clock period frame sync is selected. See Figure 8-7 for examples of frame length selection. DSP56374 Users Guide, Rev. 1.2 8-14 Freescale Semiconductor...
Page 115: Tcr Transmit Frame Sync Relative Timing (Tfsr) - Bit 16
(TFSL=0). When TFSR is cleared the word length frame sync occurs together with the first bit of the data word of the first slot. When TFSR is set the word length frame sync starts one serial clock cycle earlier, i.e., together with the last bit of the previous data word. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 116: Tcr Transmit Zero Padding Control (Padc) - Bit 17
Figure 8-8). The PDRC register provides additional clocking options by allowing the use of EXTAL as the clock source to the ESAI receiver as shown in Table 8-1. (Also see Figure 8-21). DSP56374 Users Guide, Rev. 1.2 8-16 Freescale Semiconductor...
Page 117: Rccr Receiver Prescale Modulus Select (Rpm7-Rpm0) - Bits 7-0
RFP3-RFP0 bits specify an additional division ration in the clock divider chain. See Table 8-6 for the specification of the divide ratio. The ESAI high frequency generator functional diagram is shown in Figure 8-3. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 8-17...
Page 118: Rccr Receiver Clock Polarity (Rckp) - Bit 18
In the synchronous mode when RCKD is set, the SCKR pin becomes the OF0 output flag. If RCKD is cleared, the SCKR pin becomes the IF0 input flag. See Figure 8-1 Figure 8-7. Table 8-7. SCKR Pin Definition Table Control Bits SCKR PIN RCKD SCKR input SCKR output DSP56374 Users Guide, Rev. 1.2 8-18 Freescale Semiconductor...
Page 119: Rccr Receiver Frame Sync Signal Direction (Rfsd) - Bit 22
The receivers are enabled in this register (0,1,2 or 3 receivers can be enabled) if the input data pin is not used by a transmitter. Operating modes are also selected in this register. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 120: Rcr Esai Receiver 0 Enable (Re0) - Bit 0
RCR Receiver Shift Direction (RSHFD) - Bit 6 The RSHFD bit causes the receiver shift registers to shift data in MSB first when RSHFD is cleared or LSB first when RSHFD is set (see Figure 8-13 Figure 8-14). DSP56374 Users Guide, Rev. 1.2 8-20 Freescale Semiconductor...
Page 121: Rcr Receiver Word Alignment Control (Rwa) - Bit 7
8-11. See also the ESAI data path programming model in Figure 8-13 Figure 8-14. Table 8-11. ESAI Receive Slot and Word Length Selection RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 SLOT LENGTH WORD LENGTH DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 8-21...
Page 122: Rcr Receiver Frame Sync Length (Rfsl) - Bit 15
Note that to leave the personal reset state by clearing RPR, the procedure described in Section 8.6, ESAI Initialization Examples should be followed. DSP56374 Users Guide, Rev. 1.2 8-22 Freescale Semiconductor...
Page 123: Rcr Receive Exception Interrupt Enable (Reie) - Bit 20
OF0, and data present in the OF0 bit is written to the OF0 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 124: Saicr Serial Output Flag 1 (Of1) - Bit 1
23 in the transmit and receive shift registers. NOTE While ALC is set, 20-bit and 24-bit words may not be used, and word length control should specify 8-, 12- or 16-bit words; otherwise, results are unpredictable. DSP56374 Users Guide, Rev. 1.2 8-24 Freescale Semiconductor...
Page 125: Esai Status Register (Saisr)
The Status Register (SAISR) is a read-only status register used by the DSP to read the status and serial input flags of the ESAI. See Figure 8-12. The status bits are described in the following paragraphs. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 8-25...
Page 126: Saisr Serial Input Flag 0 (If0) - Bit 0
ROE is set. Hardware, software, ESAI individual and STOP reset clear ROE. ROE is also cleared by reading the SAISR with ROE set, followed by reading all the enabled receive data registers. DSP56374 Users Guide, Rev. 1.2 8-26 Freescale Semiconductor...
Page 127: Saisr Receive Data Register Full (Rdf) - Bit 8
TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TEDE is set. Hardware, software, ESAI individual and STOP reset clear TEDE. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 128: Saisr Transmit Odd-Data Register Empty (Tode) - Bit 17
1. Data is sent MSB first if TSHFD=0. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown. 4. Data word is left-aligned (TWA=0,PADC=0). Figure 8-13. ESAI Data Path Programming Model ([R/T]SHFD=0) DSP56374 Users Guide, Rev. 1.2 8-28 Freescale Semiconductor...
Page 129: Esai Receive Shift Registers
LSB first if RSHFD=1. Data is transferred to the ESAI receive data registers after 8, 12, 16, 20, 24, or 32 serial clock cycles were counted, depending on the slot length control bits in the RCR register. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 130: Esai Receive Data Registers (Rx3, Rx2, Rx1, Rx0)
N. TS11 TS10 TS15 TS14 TS13 TS12 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 8-15. TSMA Register DSP56374 Users Guide, Rev. 1.2 8-30 Freescale Semiconductor...
Page 131: Receive Slot Mask Registers (Rsma, Rsmb)
N. RS11 RS10 RS15 RS14 RS13 RS12 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 8-17. RSMA Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 8-31...
Page 132: Operating Modes
The DSP programmer must use an individual ESAI reset when changing the ESAI control registers (except for TEIE, REIE, TLIE, RLIE, TIE, RIE, TE0-TE5, RE0-RE3) to ensure proper operation of the interface. DSP56374 Users Guide, Rev. 1.2 8-32 Freescale Semiconductor...
Page 133: Esai Interrupt Requests
In either case, the transfers are periodic. The frame sync signal indicates the first time slot in the frame. Network mode is typically used in time division multiplexed (TDM) networks of codecs, DSPs with multiple words per frame, or multi-channel devices. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 134: Synchronous/Asynchronous Operating Modes
Flag 1 (FSR pin) is enabled when the pin is not configured as external transmitter buffer enable (TEBE=0) and its direction is selected by RFSD, RFSD=1 for output and RFSD=0 for input. Flag 2 (HCKR pin) direction is selected by RHCKD, RHCKD=1 for output and RHCKD=0 for input. DSP56374 Users Guide, Rev. 1.2 8-34 Freescale Semiconductor...
Page 135: Gpio - Pins And Registers
Table 8-12 describes the port-pin configurations. Hardware and software reset clear all PRRC bits. Table 8-12. PCRC and PRRC Bits Functionality PDC[i] PC[i] Port Pin[i] Function Disconnected GPIO input GPIO output ESAI DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 8-35...
Page 136: Port C Data Register (Pdrc)
Port E (ESAI_1) GPIO - Pins and Registers The GPIO functionality of the ESAI_1 port is controlled by three registers: Port E Control register (PCRE), Port E Direction register (PRRE) and Port E Data register (PDRE). DSP56374 Users Guide, Rev. 1.2 8-36 Freescale Semiconductor...
Page 137: Port E Control Register (Pcre)
PD[i] bit will reflect the value present on this pin. If a port pin [i] is configured as a GPIO output, the value written into the corresponding PD[i] bit will be reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PD[i] bit is not reset and contains undefined data. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 8-37...
Page 138: Esai Initialization Examples
The receiver section should be in its personal reset state (RPR = 1). • Configure the control registers RCCR and RCR according to the operating mode, making sure to clear the receiver enable bits (RE0 - RE3). RPR must remain set. DSP56374 Users Guide, Rev. 1.2 8-38 Freescale Semiconductor...
Page 139 Take the receiver section out of the personal reset state by clearing RPR. • Enable the receivers by setting their RE bits. • From now on the receivers are operating and can be serviced either by polling, interrupts, or DMA. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 8-39...
Page 140 Enhanced Serial Audio Interface (ESAI) Notes DSP56374 Users Guide, Rev. 1.2 8-40 Freescale Semiconductor...
Page 141: Overview
Triple Timer Module The timers in the DSP56374 internal triple timer module act as timed pulse generators or as pulse-width modulators. Each of the three timers has a single signal (TIOx) that can function as a GPIO signal or as a timer signal. These three timers can also function as event counters to capture an event or measure the width or period of a signal.
Page 142: Operation
Configure the control register (TCSR) to set the timer operating mode. Set the interrupt enable bits as needed for the application. Configure other registers: Timer Prescaler Load Register (TPLR), Timer Load Register (TLR), and Timer Compare Register (TCPR) as needed for the application. Enable the timer by setting the TCSR[TE] bit. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 143: Timer Exceptions
9.3.1 Triple Timer Modes For all triple timer modes, the following points are true: • The TCSR[TE] bit is set to clear the counter and enable the timer. Clearing TCSR[TE] disables the timer. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 144: Timer Gpio (Mode 0)
M = write compare Clock (CLK/2 or prescale CLK) N + 1 N + 1 Counter (TCR) TCPR TCF (Compare Interrupt if TCIE = 1) Figure 9-3. Timer Mode (TRM = 1) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 145: Timer Pulse (Mode 1)
The TLR value in the TCPR sets the delay between starting the timer and generating the output pulse. To generate successive output pulses with a delay of X clock cycles between signals, set the TLR value to X/2 and set the TCSR[TRM] bit. This process repeats until the timer is disabled. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 146: Pulse Mode (Trm = 1)
Counter (TCR) TCPR TCF (Compare Interrupt if TCIE = 1) TIO pin (INV = 0) pulse width = timer clock period TIO pin (INV = 1) Figure 9-5. Pulse Mode (TRM = 1) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 147: Timer Toggle (Mode 2)
TIO signal. To generate output signals with a delay of X clock cycles between toggles, set the TLR value to X/2, and set the TCSR[TRM] bit. This process repeats until the timer is disabled (that is, TCSR[TE] is cleared). DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 148: Toggle Mode, Trm = 1
First toggle = M - N clock periods Second and later toggles = 2 clock periods TIO pin (INV = 1) TOF (Overflow Interrupt if TCIE = 1) Figure 9-8. Toggle Mode, TRM = 0 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 149: Timer Event Counter (Mode 3)
The timer clock signal can be taken from either the TIO input signal or the prescaler clock output. If an external clock is used, it is synchronized internally to the internal clock, and its frequency must be less than the DSP56374 internal operating frequency divided by 4.
Page 150: Signal Measurement Modes
TLR value on the first timer clock received following the next valid transition on the TIO input signal, and the count resumes. If TCSR[TRM] is cleared, the counter continues to increment on each timer clock. This process repeats until the timer is disabled. DSP56374 Users Guide, Rev. 1.2 9-10 Freescale Semiconductor...
Page 151: Pulse Width Measurement Mode, Trm = 1
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO stops the counter and loads TCR with the count. Figure 9-12. Pulse Width Measurement Mode, TRM = 0 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 9-11...
Page 152: Measurement Input Period (Mode 5)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO loads TCR with count and the counter with N. Figure 9-13. Period Measurement Mode, TRM = 1 DSP56374 Users Guide, Rev. 1.2 9-12 Freescale Semiconductor...
Page 153: Measurement Capture (Mode 6)
(1 to 0) or low-to-high (0 to 1) transition of the external clock signals the end of the timing period. If the INV bit is set, a high-to-low transition signals the end of the timing period. If INV is cleared, a low-to-high transition signals the end of the timing period. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 154: Pulse Width Modulation (Pwm, Mode 7)
($FFFFFF − TLR + 1). For a 50 percent duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1)/2. NOTE The value in TCPR must be greater than the value in TLR. DSP56374 Users Guide, Rev. 1.2 9-14 Freescale Semiconductor...
Page 155: Pulse Width Modulation Toggle Mode, Trm = 1
TCF (Compare Interrupt if TCIE = 1) TCF (Overflow Interrupt if TDIE = 1) TIO pin (INV = 0) TIO pin (INV = 1) Pulse width Period Figure 9-16. Pulse Width Modulation Toggle Mode, TRM = 1 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 9-15...
Page 156: Watchdog Modes
TCPR, if the TCSR[TRM] bit is set, the counter is loaded with the TLR value on the next timer clock and the count resumes. Therefore TRM = 1 is not useful for watchdog functions. If the TCSR[TRM] bit is cleared, the counter continues to increment on DSP56374 Users Guide, Rev. 1.2 9-16...
Page 157: Watchdog Toggle (Mode 10)
In Mode 9, internal logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after the hardware RESET signal is asserted. This convention ensures that a valid RESET signal is generated when the TIO signal resets the DSP56374.
Page 158: Reserved Modes
Timer behavior during stop — During execution of the STOP instruction, the timer clocks are disabled, timer activity stops, and the TIO signals are disconnected. Any external changes that happen to the TIO signals are ignored when the DSP56374 is in stop state.
Page 159: Timer Prescaler Load Register (Tplr)
PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12 PL11 PL10 — Reserved bit. Read as 0. Write to 0 for future compatibility DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 9-19...
Page 160: Timer Prescaler Count Register (Tpcr)
TIO signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be lower than the DSP56374 internal operating frequency divided by 4 (that is, CLK/4).
Page 161: Timer Control/Status Register (Tcsr)
DO bit is inverted when written to the TIO signal. When the INV bit is cleared, the value of the DO bit is written directly to the TIO signal. When GPIO mode is disabled, writing to the DO bit has no effect. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 9-21...
Page 162 (the TCSR[TE] bit is cleared). The timer is in GPIO mode. DSP56374 Users Guide, Rev. 1.2 9-22 Freescale Semiconductor...
Page 163 Reserved — — Reserved — — Reserved — — Note 1: The GPIO function is enabled only if all of the TC[3–0] bits are 0. Reserved. Write to zero for future compatibility. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 9-23...
Page 164 — — Period is measured Period is measured between the rising edges between the falling edges of the input signal. of the input signal. — — DSP56374 Users Guide, Rev. 1.2 9-24 Freescale Semiconductor...
Page 165: Timer Load Register (Tlr)
When the timer is in measurement mode, the TIO signal is used for the input signal. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 166 Triple Timer Module Notes DSP56374 Users Guide, Rev. 1.2 9-26 Freescale Semiconductor...
Page 167: Watchdog Timer Module
Note the watchdog timer registers are accessed via the BIU bus and thus require that the BIU be enabled. The BIU may be enabled by writing $01FFFF to the BCR register (x:$FFFFFB). DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor 10-1...
Page 168: Description Of Registers
1 = Watchdog timer is stopped in DEBUG mode. Watchdog Enable (WEN) 0 = Watchdog timer is disabled. The TIO1/WDT pin functions as a TIO1 pin. 1 = Watchdog timer is enabled. The TIO1/WDT pin functions as a WDT pin. DSP56374 Users Guide, Rev. 1.2 10-2 Freescale Semiconductor...
Page 169: Watchdog Counter & Wcntr Register
Writing to WMR immediately loads the new modulus value into the watchdog counter. The new value is also used at all subsequent reloads. Reading the WMR register returns the value in the modulus register. DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 170: Watchdog Service Register (Wsr)
10.5.3 STOP MODE The Fosc is assumed to be stopped in STOP mode. The watchdog timer does not function in stop mode. DSP56374 Users Guide, Rev. 1.2 10-4 Freescale Semiconductor...
Page 171: Appendix A Bootstrap Source Code
DSP56374 Bootstrap Program Appendix A Bootstrap Source Code DSP56374 Bootstrap Program ; BOOTSTRAP CODE FOR DSP56374 Rev. 0 silicon - ; (C) Copyright 2003- Freescale Semiconductor, Inc. (formerly Motorola) ; Revision 0.0 19 Sep 2003 - ; Modified from 56371Boot.asm: ;...
Page 172 ; The program words will be stored in contiguous PRAM memory locations starting ; at the specified starting address. ; After storing the program words, program execution starts from the same ; address where loading started. mode5: mode6: mode7: DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 173 ; The following modes are reserved, some of which are used for internal testing ; Operation mode MD:MC:MB:MA=0000 is reserved ; Operation mode MD:MC:MB:MA=0001 is reserved ; Operation mode MD:MC:MB:MA=0011 is reserved ; Operation mode MD:MC:MB:MA=0100 is reserved ; Operation mode MD:MC:MB:MA=1000 is reserved DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 174 ; This code fills the unused bootstrap rom locations with their address dup STRAP_START+$200-* dc * endm ;======================================================================== ; Serial EEPROM Boot Loader ;======================================================================== ; This code fills the unused bootstrap rom locations with their address dup $FF01B0-* dc * endm ;======================================================================== endsec DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 175: Using The Serial Eeprom Boot Mode
Assuming the EEPROM address starts at 0: - EEPROM Byte expected at DSP Example Address PstartAddress2 PstartAddress1 PstartAddress0 XstartAddress2 XstartAddress1 XstartAddress0 YstartAddress2 YstartAddress1 YstartAddress0 PdataLength2 PdataLength1 PdataLength0 XdataLength2 XdataLength1 XdataLength0 YdataLength2 YdataLength1 YdataLength0 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 176 ;ROM boot area. HCKR $FFFF90 ;SHI Clock Control Register. HCSR $FFFF91 ;SHI Control/Status Register. $FFFF94 ;SHI Receive Data FIFO $FFFF93 ;SHI Transmit Data Register qROM define mHPORT "x" ;need to change to X for 374 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 177 #PH0_CS,mHPORT:PDRH ; Set CS to low ;*** Send Read Command*** ; Read Command = 3 movep #$30000,x:HTX brclr #19,x:HCSR,* movep x:HRX,a1 ;*** Send Address Key *** brclr #15,x:HCSR,* movep #$0,x:HTX ; Start from MSB:0 brclr #19,x:HCSR,* movep x:HRX,a1 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 178 ;*** Get Data of X Memory *** x1,_endofX GetWordSPI move a1,x:(r1)+ _endofX ;*** Get Data of Y Memory *** y1,_endofY GetWordSPI move a1,y:(r2)+ _endofY GetWordSPI move a1,r0 GLOBAL GetWordSPI GetWordSPI: brclr #19,x:HCSR,* move x:HRX,a1 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 179 ; 8 - signal no more data in EEPROM with $55 $55 $55 sequence ; 9 - when master DSP sees $55 $55 $55, it will indicate end of recieve by setting the HIDLE bit SHIReset movep #$FF0000,X:HTX; Generate stop event if error #2560 #2560 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 180 - YdataLength0 - data in P, X and Y order - must make up whole 24 bit words - PstartAddress2 - PstartAddress1 - PstartAddress0 00-final word is start address of program to run DSP56374 Users Guide, Rev. 1.2 A-10 Freescale Semiconductor...
Page 181 ;Get Y length move a1,r6 ;Store Y length ;************************************** ;*** Get data from EPROM *** ;Get length of P data r4,EndofP GetWord move a1,p:(r0)+ EndofP: ;Get length of X data r5,EndofX GetWord move a1,x:(r1)+ DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor A-11...
Page 182 ;Shift 2 MSBs to 2 LSBs getByte0: brset #19,X:HCSR,ReadByte0 ;Read byte received or wait until FIFO full getByte0 ReadByte0: move x:HRX,a1 ;Move byte 0 into x1 #16,a,a move a1,x1 ;Shift 2 MSBs to 2 LSBs DSP56374 Users Guide, Rev. 1.2 A-12 Freescale Semiconductor...
Page 183 ; Get P Data Length ReadData move a1,x1 ; Get X Data Length ReadData move a1,y1 ; Get Y Data Length y0,_endofPGPIO ReadData move a1,p:(r0)+ _endofPGPIO x1,_endofXGPIO ReadData move a1,x:(r1)+ _endofXGPIO DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor A-13...
Page 184 ; Set to /64 for max crystal value (i.e., 25MHz/(8*8) = 390625 ; Enable wide spike filter movep #$003040,X:HCKR ;*** Check HTX is empty i.e., HTDE=1 *** brclr #15,X:HCSR,* move #$008243,X:HCSR #256 DSP56374 Users Guide, Rev. 1.2 A-14 Freescale Semiconductor...
Page 185: Appendix B Equates
; Trap I_NMI I_VEC+$0A ; Non Maskable Interrupt ;------------------------------------------------------------------------ ; Interrupt Request Pins ;------------------------------------------------------------------------ I_IRQA I_VEC+$10 ; IRQA I_IRQB I_VEC+$12 ; IRQB I_IRQC I_VEC+$14 ; IRQC I_IRQD I_VEC+$16 ; IRQD ;------------------------------------------------------------------------ ; DMA Interrupts DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 186 ;------------------------------------------------------------------------ ; Timer Interrupts ;------------------------------------------------------------------------ I_TIM0C EQU I_VEC+$54 ; TIMER 0 compare I_TIM0OF EQU I_VEC+$56 ; TIMER 0 overflow I_TIM1C EQU I_VEC+$58 ; TIMER 1 compare I_TIM1OF EQU I_VEC+$5A ; TIMER 1 overflow DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 187 ;------------------------------------------------------------------------ ; INTERRUPT ENDING ADDRESS ;------------------------------------------------------------------------ I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space ;------------------ end of intequ.asm ------------------------ ;********************************************************************************* EQUATES for DSP56374 I/O registers and ports Last update: July 2, 2003 ;********************************************************************************* page 132,55,0,0,0 ioequ ident ;------------------------------------------------------------------------ EQUATES for I/O Port Programming DSP56374 Users Guide, Rev.
Page 188 ; DMA2 Interrupt Priority Level (low) M_D2L1 ; DMA2 Interrupt Priority Level (high) M_D3L $C0000 ; DMA3 Interrupt Priority Level Mask M_D3L0 ; DMA3 Interrupt Priority Level (low) M_D3L1 ; DMA3 Interrupt Priority Level (high) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 189 M_DSR1 $FFFFEB ; X space: DMA1 Source Address Register M_DDR1 $FFFFEA ; X space: DMA1 Destination Address Register M_DCO1 $FFFFE9 ; X space: DMA1 Counter M_DCR1 $FFFFE8 ; X space: DMA1 Control Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 190 ; DMA Channel Priority Level (high) M_DTM $380000 ; DMA Transfer Mode Mask (DTM2-DTM0) M_DTM0 ; DMA Transfer Mode 0 M_DTM1 ; DMA Transfer Mode 1 M_DTM2 ; DMA Transfer Mode 2 M_DIE ; DMA Interrupt Enable bit DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 191 ; PreDivider Factor Bits Mask (PD0-PD3) M_PD0 ; PreDivider Factor bit 0 M_PD1 ; PreDivider Factor bit 1 M_PD2 ; PreDivider Factor bit 2 M_PD3 ; PreDivider Factor bit 3 M_PD4 ; PreDivider Factor bit 4 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 192 OMR M_MA ; Operating Mode A M_MB ; Operating Mode B M_MC ; Operating Mode C M_MD ; Operating Mode D M_SD ; Stop Delay M_MS ;Memory Switch Mode DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 193 ; DAX Underrun Error Interrupt Enable (XUIE) M_XBIE ; DAX Block Transferred Interrupt Enable (XBIE) M_XCS0 ; DAX Clock Input Select 0 (XCS0) M_XCS1 ; DAX Clock Input Select 1 (XCS1) M_XSB ; DAX Start Block (XSB) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 194 ; SHI Divider Modulus Select (HDM4) M_HDM3 ; SHI Divider Modulus Select (HDM3) M_HDM2 ; SHI Divider Modulus Select (HDM2) M_HDM1 ; SHI Divider Modulus Select (HDM1) M_HDM0 ; SHI Divider Modulus Select (HDM0) DSP56374 Users Guide, Rev. 1.2 B-10 Freescale Semiconductor...
Page 195 M_RX0 $FFFFA8 ; X space: ESAI Receive Data Register 0 (RX0) M_TSR $FFFFA6 ; X space: ESAI Time Slot Register (TSR) M_TX5 $FFFFA5 ; X space: ESAI Transmit Data Register 5 (TX5) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor B-11...
Page 196 ; ESAI M_TS28 ; ESAI M_TS27 ; ESAI M_TS26 ; ESAI M_TS25 ; ESAI M_TS24 ; ESAI M_TS23 ; ESAI M_TS22 ; ESAI M_TS21 ; ESAI M_TS20 ; ESAI M_TS19 ; ESAI DSP56374 Users Guide, Rev. 1.2 B-12 Freescale Semiconductor...
Page 197 ; ESAI M_RPM4 ; ESAI M_RPM3 ; ESAI M_RPM2 ; ESAI M_RPM1 ; ESAI M_RPM0 ; ESAI RCR Register bits M_RLIE ; ESAI M_RIE ; ESAI M_REDIE EQU ; ESAI M_REIE ; ESAI DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor B-13...
Page 198 ; ESAI M_TPM1 ; ESAI M_TPM0 ; ESAI TCR Register bits M_TLIE ; ESAI M_TIE ; ESAI M_TEDIE EQU ; ESAI M_TEIE ; ESAI M_TPR ; ESAI M_PADC ; ESAI M_TFSR ; ESAI DSP56374 Users Guide, Rev. 1.2 B-14 Freescale Semiconductor...
Page 199 $FFFF8F ; X space: TIMER0 Control/Status Register M_TLR0 $FFFF8E ; X space: TIMER0 Load Reg M_TCPR0 EQU $FFFF8D ; X space: TIMER0 Compare Register M_TCR0 $FFFF8C ; X space: TIMER0 Count Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor B-15...
Page 200 M_PS0 EQU 21 M_PS1 EQU 22 ;----------------------------------------------------------------------- EQUATES for EFCOP ;------------------------------------------------------------------------ M_EFCOP EQU $FFFFB0 M_FDIR M_EFCOP+$0 ; Y space: EFCOP Data Input Register M_FDOR M_EFCOP+$1 ; Y space: EFCOP Data Output Register DSP56374 Users Guide, Rev. 1.2 B-16 Freescale Semiconductor...
Page 201 ; Watchdog Timer Modulus bit 3 mask M_WM4 EQU 4 ; Watchdog Timer Modulus bit 4 mask M_WM5 EQU 5 ; Watchdog Timer Modulus bit 5 mask M_WM6 EQU 6 ; Watchdog Timer Modulus bit 6 mask DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor B-17...
Page 202 ; Watchdog Timer Service bit 13 mask M_WS14 EQU 14 ; Watchdog Timer Service bit 14 mask M_WS15 EQU 15 ; Watchdog Timer Service bit 15 mask ;------------------ end of ioequ.asm ------------------------ DSP56374 Users Guide, Rev. 1.2 B-18 Freescale Semiconductor...
Page 203: Appendix C Programmer's Reference
Interrupt Priorities Figure C-3. lists the priorities of specific interrupts within interrupt priority levels. C.1.4 Programming Sheets The remaining figures describe major programmable registers on the DSP56374. C.1.5 Internal I/O Memory Map Table C-1. Internal I/O Memory Map (X Memory) Peripheral...
Page 204 X:$FFFFC5 RESERVED X:$FFFFC4 RESERVED X:$FFFFC3 RESERVED X:$FFFFC2 RESERVED X:$FFFFC1 RESERVED X:$FFFFC0 RESERVED PORT C X:$FFFFBF PORT C CONTROL REGISTER (PCRC) X:$FFFFBE PORT C DIRECTION REGISTER (PRRC) X:$FFFFBD PORT C GPIO DATA REGISTER (PDRC) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 205 X:$FFFF96 RESERVED X:$FFFF95 RESERVED X:$FFFF94 SHI RECEIVE FIFO (HRX) X:$FFFF93 SHI TRANSMIT REGISTER (HTX) X:$FFFF92 SHI I C SLAVE ADDRESS REGISTER (HSAR) X:$FFFF91 SHI CONTROL/STATUS REGISTER (HCSR) X:$FFFF90 SHI CLOCK CONTROL REGISTER (HCKR) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 206 Y:$FFFFF4 RESERVED Y:$FFFFF3 RESERVED Y:$FFFFF2 RESERVED Y:$FFFFF1 RESERVED Y:$FFFFF0 RESERVED RESERVED Y:$FFFFEF RESERVED Y:$FFFFEE RESERVED Y:$FFFFED RESERVED Y:$FFFFEC RESERVED Y:$FFFFEB RESERVED Y:$FFFFEA RESERVED Y:$FFFFE9 RESERVED Y:$FFFFE8 RESERVED Y:$FFFFE7 RESERVED Y:$FFFFE6 RESERVED Y:$FFFFE5 RESERVED DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 207 Watchdog Count Register (WCNTR) Y:$FFFFC1 Watchdog Modulus Register (WMR) Y:$FFFFC0 Watchdog Control Register (WCR) RESERVED Y:$FFFFBF RESERVED Y:$FFFFBE RESERVED Y:$FFFFBD RESERVED Y:$FFFFBC RESERVED Y:$FFFFBB RESERVED Y:$FFFFBA RESERVED Y:$FFFFB9 RESERVED Y:$FFFFB8 RESERVED Y:$FFFFB7 RESERVED DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 208 Patch Address 3 Y:$FFFFA2 Patch Address 2 Y:$FFFFA1 Patch Address 1 Y:$FFFFA0 Patch Address 0 PORT E Y:$FFFF9F PORT E CONTROL REGISTER (PCRE) Y:$FFFF9E PORT E DIRECTION REGISTER(PRRE) Y:$FFFF9D PORT E GPIO DATA REGISTER(PDRE) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 209: Interrupt Vector Addresses
ESAI_1 TRANSMIT DATA REGISTER 2 (TX2_1) Y:$FFFF81 ESAI_1 TRANSMIT DATA REGISTER 1 (TX1_1) Y:$FFFF80 ESAI_1 TRANSMIT DATA REGISTER 0 (TX0_1) C.1.6 Interrupt Vector Addresses Table C-3. DSP56374 Interrupt Vectors Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$00 Hardware RESET...
Page 210 Introduction Table C-3. DSP56374 Interrupt Vectors (continued) Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$12 0 - 2 IRQB VBA:$14 0 - 2 IRQC VBA:$16 0 - 2 IRQD VBA:$18 0 - 2 DMA Channel 0 VBA:$1A 0 - 2...
Page 211 Introduction Table C-3. DSP56374 Interrupt Vectors (continued) Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$5A 0 - 2 TIMER1 Overflow VBA:$5C 0 - 2 TIMER2 Compare VBA:$5E 0 - 2 TIMER2 Overflow VBA:$60 0 - 2 RESERVED VBA:$62...
Page 212: Interrupt Source Priorities (Within An Ipl
Interrupt Source Priorities (within an IPL) Table C-3. DSP56374 Interrupt Vectors (continued) Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$A2 0 - 2 RESERVED VBA:$A4 0 - 2 RESERVED VBA:$A6 0 - 2 RESERVED VBA:$A8 0 - 2...
Page 213: Programming Sheets
ESAI_1 Transmit Last Slot ESAI_1 Transmit Even Data Lowest ESAI_1 Transmit Data Programming Sheets The worksheets shown on the following pages contain listings of major programmable registers for the DSP56374. The programming sheets are grouped into the following order: • Central Processor •...
Page 214 15 14 13 12 11 10 CP1 CP0 RM Extended Mode Register (MR) Mode Register (MR) Condition Code Register (CCR) = Reserved, Program as 0 Status Register (SR) Read/Write Reset = $C00300 Figure C-1. Status Register (SR) DSP56374 Users Guide, Rev. 1.2 C-12 Freescale Semiconductor...
Page 215 Extended Chip Operating Chip Operating Mode Status Register (SCS) Mode Register (COM) Register (COM) Operating Mode Register (OMR) Read/Write Reset = $00030X = Reserved, Program as 0 Figure C-2. Operating Mode Register (OMR) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-13...
Page 216 Programming Sheets Date: Application: Programmer: Figure C-3. Interrupt Priority Register–Core (IPR–C) DSP56374 Users Guide, Rev. 1.2 C-14 Freescale Semiconductor...
Page 217 Programming Sheets Date: Application: Programmer: Figure C-4. Interrupt Priority Register – Peripherals (IPR–P) DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-15...
Page 218 Programming Sheets Date: Application: Programmer: DSP56374 Users Guide, Rev. 1.2 C-16 Freescale Semiconductor...
Page 219 Programming Sheets Date: Application: Programmer: DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-17...
Page 220 Programming Sheets Date: Application: Programmer: Figure C-5. SHI Slave Address and Clock Control Registers DSP56374 Users Guide, Rev. 1.2 C-18 Freescale Semiconductor...
Page 221 Programming Sheets Date: Application: Programmer: Figure C-6. SHI Host Control/Status Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-19...
Page 222 Programming Sheets Date: Application: Programmer: Figure C-7. ESAI Transmit Clock Control Register DSP56374 Users Guide, Rev. 1.2 C-20 Freescale Semiconductor...
Page 223 Programming Sheets Date: Application: Programmer: Figure C-8. ESAI Transmit Control Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-21...
Page 224 Programming Sheets Date: Application: Programmer: Figure C-9. ESAI Receive Clock Control Register DSP56374 Users Guide, Rev. 1.2 C-22 Freescale Semiconductor...
Page 225 Programming Sheets Date: Application: Programmer: Figure C-10. ESAI Receive Control Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-23...
Page 226 Programming Sheets Date: Application: Programmer: Figure C-11. ESAI Common Control Register DSP56374 Users Guide, Rev. 1.2 C-24 Freescale Semiconductor...
Page 227 Programming Sheets Date: Application: Programmer: Figure C-12. ESAI Status Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-25...
Page 228 Programming Sheets Date: Application: Programmer: Figure C-13. ESAI_1 Transmit Clock Control Register DSP56374 Users Guide, Rev. 1.2 C-26 Freescale Semiconductor...
Page 229 Programming Sheets Date: Application: Programmer: Figure C-14. ESAI_1 Transmit Control Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-27...
Page 230 Programming Sheets Date: Application: Programmer: Figure C-15. ESAI_1 Receive Clock Control Register DSP56374 Users Guide, Rev. 1.2 C-28 Freescale Semiconductor...
Page 231 Programming Sheets Date: Application: Programmer: Figure C-16. ESAI_1 Receive Control Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-29...
Page 232 Programming Sheets Date: Application: Programmer: Figure C-17. ESAI_1 Common Control Register DSP56374 Users Guide, Rev. 1.2 C-30 Freescale Semiconductor...
Page 233 Programming Sheets Date: Application: Programmer: Figure C-18. ESAI_1 Status Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-31...
Page 234 Current Value of Prescaler Counter (PC [0:20]) Timer Prescaler Count Register = Reserved, Program as 0 X:$FFFF82 Read Only Reset = $000000 Figure C-19. Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR) DSP56374 Users Guide, Rev. 1.2 C-32 Freescale Semiconductor...
Page 235 Note that for Timers 2, TC (3:0) = 0000 is the only valid combination. TCSR1 X:$FFFF8B Read/Write All other combinations are reserved. TCSR2 X:$FFFF87 Read/Write Reset = $000000 Figure C-20. Timer Control/Status Register DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-33...
Page 236 15 14 13 12 11 10 9 Timer Count Value Timer Count Register TCR0 X:$FFFF8C Read Only TCR1 X:$FFFF88 Read Only TCR2 X:$FFFF84 Read Only Reset = $000000 Figure C-21. Timer Load, Compare and Count Registers DSP56374 Users Guide, Rev. 1.2 C-34 Freescale Semiconductor...
Page 237 19 18 17 16 15 14 13 12 11 10 9 WS14 WS12 WS11 WS10 WS15 WS13 = Reserved, Program as 0 Y:$FFFFC3 Watchdog Service Register (WSR) Write Only Reset = Undefined DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-35...
Page 238 If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n Figure C-22. GPIO Port C DSP56374 Users Guide, Rev. 1.2 C-36 Freescale Semiconductor...
Page 239 If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n Figure C-23. GPIO Port E DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-37...
Page 240 If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n Figure C-24. GPIO Port G DSP56374 Users Guide, Rev. 1.2 C-38 Freescale Semiconductor...
Page 241 If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n Figure C-25. GPIO Port H DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor C-39...
Page 242 Programming Sheets DSP56374 Users Guide, Rev. 1.2 C-40 Freescale Semiconductor...
Page 243: Appendix Dbsdl
0); io_gnd: linkage bit_vector(1 downto 0); core_vdd: linkage bit_vector(3 downto 0); core_gnd: linkage bit_vector(3 downto 0); plla_vdd: linkage bit; plla_gnd: linkage bit; pllp_vdd: linkage bit; DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 244 STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of DSP56374 : entity is "STD_1149_1_2001"; attribute PIN_MAP of DSP56374 : entity is PHYSICAL_PIN_MAP; constant DSP56374_52PIN : PIN_MAP_STRING := "io_vdd: (40, 14, 1), " & "moda_irqa: 2, " & "modb_irqb: 3, "...
Page 245 TAP_SCAN_MODE of tms : signal is true; attribute TAP_SCAN_CLOCK of tck : signal is (20.0e6, BOTH); attribute COMPLIANCE_PATTERNS of DSP56374 : entity is "(scan) (0)"; attribute INSTRUCTION_LENGTH of DSP56374 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56374 : entity is "EXTEST (0000)," &...
Page 246 (BC_2, *, internal, 1)," & "69 (BC_7, sdo3_sdi2_pc8, bidir, 70, 1, Z)," & "70 (BC_2, *, control, 1)," & "71 (BC_7, sdo2_sdi3_pc9, bidir, 72, 1, Z)," & "72 (BC_2, *, control, 1)," & DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 247 [ccell dis rslt] "100 (BC_7, tio0_pb0, bidir, 101, 1, Z)," & "101 (BC_2, *, control, 1)," & "102 (BC_2, *, internal, 1)," & "103 (BC_2, *, internal, 1)"; end DSP56374; DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 248: 80-Pin Bsdl
DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 249 STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of DSP56374 : entity is "STD_1149_1_2001"; attribute PIN_MAP of DSP56374 : entity is PHYSICAL_PIN_MAP; constant DSP56374_80PIN : PIN_MAP_STRING := "io_vdd: (61, 47, 21, 1), " & "moda_irqa: 2, " &...
Page 250 TAP_SCAN_MODE of tms : signal is true; attribute TAP_SCAN_CLOCK of tck : signal is (20.0e6, BOTH); attribute COMPLIANCE_PATTERNS of DSP56374 : entity is "(scan) (0)"; attribute INSTRUCTION_LENGTH of DSP56374 : entity is 4; DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor...
Page 251 (1010)," & "SHI_FILTER_TEST (1101)," & "BYPASS (1111)"; attribute INSTRUCTION_CAPTURE of DSP56374 : entity is "0001"; attribute INSTRUCTION_PRIVATE of DSP56374 : entity is "PLL_COMMAND, MBIST_COMMAND, MBIST_ACCESS, SHI_FILTER_TEST "; attribute IDCODE_REGISTER of DSP56374 : entity is "00000001110000000011000000011101"; attribute REGISTER_ACCESS of DSP56374 : entity is "ONCE[8]...
Page 252 76, 1, Z)," & "76 (BC_2, *, control, 1)," & "77 (BC_7, sdo3_sdi2_pe8, bidir, 78, 1, Z)," & "78 (BC_2, *, control, 1)," & "79 (BC_7, sdo2_sdi3_pe9, bidir, 80, 1, Z)," & DSP56374 Users Guide, Rev. 1.2 D-10 Freescale Semiconductor...
Page 253 [ccell dis rslt] "100 (BC_7, tio0_pb0, bidir, 101, 1, Z)," & "101 (BC_2, *, control, 1)," & "102 (BC_7, gpio_pg4, bidir, 103, 1, Z)," & "103 (BC_2, *, control, 1)"; end DSP56374; DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor D-11...
Page 254 BSDL Notes DSP56374 Users Guide, Rev. 1.2 D-12 Freescale Semiconductor...
Page 255 Data Transfer Formats 13 ESAI block diagram 1 Master Mode 15 ESSI0 (GPIO) 1 Protocol for Host Write Cycle 13 ESSI1 (GPIO) 1, 3 Receive Data In Master Mode 16 EXTAL 2 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor Index-1...
Page 256 Clock Generator 2 Peripheral I/O Expansion Bus 4 Control/Status Register—DSP Side 7 Phase Detector (PD) 2 Data Size 8 Phase Locked Loop (PLL). See PLL Exception Priorities 4 PIC 4 HCKR PINIT 1 DSP56374 Users Guide, Rev. 1.2 Index-2 Freescale Semiconductor...
Page 257 Timer Control/Status Register (TCSR) 2, 21 System Stack (SS) 4 bit definitions 21 SZ register 4 Data Input (DI) 22 Data Output (DO) 21 Direction (DIR) 22 Timer 1 Inverter (INV) 22, 24 DSP56374 Users Guide, Rev. 1.2 Freescale Semiconductor Index-3...
Page 258 X Memory Data Bus (XDB) 5 X Memory Expansion Bus 5 XAB 5 XDB 5 Y Memory Address Bus (YAB) 5 Y Memory Data Bus (YDB) 5 Y Memory Expansion Bus 5 YAB 5 YDB 5 DSP56374 Users Guide, Rev. 1.2 Index-4 Freescale Semiconductor...

Freescale Semiconductor DSP56374 User Manual

Chapter 1 DSP56374 Overview

Chapter 2 Signal/Connection Descriptions

Chapter 3 Memory Configuration

Chapter 4 Core Configuration

Chapter 5 PLL and Clock Generator

Chapter 6 General Purpose Input/Output

Chapter 7 Serial Host Interface

Chapter 8 Enhanced Serial Audio Interface (ESAI)

Chapter 9

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