Ground - Freescale Semiconductor DSP56374 User Manual

IO_Vdd
MODA_IRQA_PH0
MODB_IRQB_PH1
MODC_IRQC_PH2
MODD_IRQD_PH3
Core_Vdd
Core_Gnd
HREQ_PH4
SS_HA2
SCK_SCL
MISO_SDA
MOSI_HA0
IO_Gnd
3.3 V
2.3

Ground

Ground Name
PLLA_GND(1) PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND.
PLLP_GND(1) PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLLD_GND(1) PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.
CORE_GND(4) Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
IO_GND(2) SHI, ESAI, ESAI_1, WDT and Timer I/O Ground—IO_GND is the ground for the SHI, ESAI,
ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Freescale Semiconductor
1
2
3
4
5
6
7
8
9
10
11
12
13
Filter
Figure 2-2. 52-pin Vdd Connections
Table 2-3. Grounds
Description
DSP56374 Users Guide, Rev. 1.2
39 SDO3_PC8
38 SDO2_PC9
37 SDO1_PC10
36 SDO0_PC11
35 Core_Vdd
34 Core_Gnd
33 PINIT_NMI
32 XTAL
31 EXTAL
30 PLLD_Vdd
29 PLLD_Gnd
28 PLLP_Gnd
27 PLLP_Vdd
1.25 V
Ground
2-3