Timer - Freescale Semiconductor DSP56374 User Manual

Timer

2.11 Timer
Signal
Type
Name
TIO0 Input or
Output
TIO1 Input or
Output
WDT Output
TIO2 Input or
Output
PLOCK Output
2-18
Table 2-11. Timer Signal
State during
Reset
GPIO Input Timer 0 Input/Output—When timer 0 functions as an external event
counter or in measurement mode, TIO0 is used as input. When timer 0
functions in watchdog, timer, or pulse modulation mode, TIO0 is used
as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer 0
control/status register (TCSR0). If TIO0 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input.
This pin has an internal pull-down resistor.
This input is 5 V tolerant
Watchdog Timer Timer 1 Input/Output—When timer 1 functions as an external event
Output counter or in measurement mode, TIO1 is used as input. When timer 1
functions in watchdog, timer, or pulse modulation mode, TIO1 is used
as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer
1control/status register (TCSR1). If TIO1 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input.
WDT—When this pin is configured as a hardware watchdog timer pin,
this signal is asserted low when the hardware watchdog timer counts
down to zero.
This pin has an internal pull-down resistor.
This input is 5 V tolerant
PLOCK Output Timer 2 Input/Output—When timer 2 functions as an external event
counter or in measurement mode, TIO2 is used as input. When timer 2
functions in watchdog, timer, or pulse modulation mode, TIO2 is used
as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer
control/status register (TCSR2). If TIO2 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input.
PLOCK—When this pin is configured as a PLL lock pin, this signal is
asserted high when the on-chip PLL enabled and locked and
de-asserted when the PLL enabled and unlocked. This pin is also
asserted high when the PLL is disabled.
This pin has an internal pull-down resistor.
This input is 5 V tolerant
DSP56374 Users Guide, Rev. 1.2
Signal Description
Freescale Semiconductor