Operation; Timer After Reset; Timer Initialization - Freescale Semiconductor DSP56374 User Manual

Operation

• 24-bit counter
• 24-bit read/write Timer Control and Status Register (TCSR)
• 24-bit read-only Timer Count Register (TCR)
• 24-bit write-only Timer Load Register (TLR)
• 24-bit read/write Timer Compare Register (TCPR)
• Logic for clock selection and interrupt/DMA trigger generation.
The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the timer modes and descriptions of their operations,
see Section 9.3, Operating Modes.
.
GDB
Control/Status
Register
Timer Control
Logic
TIO CLK/2
9.2 Operation
This section discusses the following timer basics:
• Reset
• Initialization
• Exceptions
9.2.1

Timer After Reset

A hardware RESET signal or software RESET instruction clears the Timer Control and Status Register for each timer, thus configuring each
timer as a GPIO. A timer is active only if the timer enable bit 0 (TCSR[TE]) in the specific timer TCSR is set.
9.2.2

Timer Initialization

To initialize a timer, do the following:
1. Ensure that the timer is not active either by sending a reset or clearing the TCSR[TE] bit.
2. Configure the control register (TCSR) to set the timer operating mode. Set the interrupt enable bits as needed for the application.
3. Configure other registers: Timer Prescaler Load Register (TPLR), Timer Load Register (TLR), and Timer Compare Register
(TCPR) as needed for the application.
4. Enable the timer by setting the TCSR[TE] bit.
9-2
24
24 24
TCSR
TLR
Load
Register
9
2
Timer interrupt/DMA request
Prescaler CLK
Figure 9-2. Timer Module Block Diagram
DSP56374 Users Guide, Rev. 1.2
24
TCR
Count
Register
24 24
24
Counter
24
TCPR
Compare
Register
24
=
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